WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE TEAM:

This team is a coveted team leading technical innovation and execution of cutting-edge AI technology both in inference and generative AI. AI Chip lead is responsible for creating micro architecture spec, enabling execution by understanding and removing design and implementation roadblocks, facilitating feature enablement, overall health of the project along with its timely execution. In this capacity, we interact with architecture, physical design, test, front end, design verification, project management, post-silicon bring-up and diagnostic teams, and occasionally software teams as well. We are responsible for analyzing past programs and inheriting best practices and improve upon them with current SOC requirements. While execution is our utmost priority, we do represent or participate in companywide discussion related to best execution strategies and methods.  

This team comprises of a few engineers who have extensive and varied experience in Design, Design for Test, Design Verification, Physical Design and Platform, to name a few among other disciplines of design process. We believe in growing engineers into successful leads and therefore credit in hiring young engineers and train them. This is a high visibility team and is well respected and recognized in the company.  Our core values are – Humility, Help and Hygiene.

THE ROLE:

There is no pre-requisite for you to have an RTL design background (as mentioned in the team introduction), you can be an AISC engineer with whatever background within hardware design execution realm and you can apply to this role. You will be responsible for creating micro architecture spec, refining flow for existing and new methodologies and initiatives. In some way you get to choose what you want to do in terms of your role and visibility. We expect you to have a lot of questions and therefore you must be self-driven to talk to other engineers, use AMD resources to find the answers. We also expect you to ask questions and engage in discussions (respectfully).  You will work with leading industry tools and design/verification/dfx/timing/power/physical design concepts to assist in developing the specification along with infrastructure flows to facilitate execution.

THE PERSON:

The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification, Design for Test, Synthesis, Static Timing Analysis, Power Verification and optimization, Physical Design aspects like Floorplan, Full chip timing, Place and Route and Utilization experiments.

While we do understand that it is very difficult to have knowledge on expected areas, the candidate should have strong foundation in digital design to pick up the necessary concepts and should strive to continuously learn on the job.

Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or any pre-silicon technical issue. Expertise in scripting(perl, tcl or python) is a must. You should be able strike a balance between collaborative problem-solving and independent solution development.   

KEY RESPONSIBILITIES:

• Study both high-level and micro architecture specifications and use Computer Architecture knowledge and background to gain an in depth understanding of new features or changes proposed in new projects.
• Automate (using scripting language) any execution flow that lacks efficiency or consumes more time to complete after discussing the overall picture and required data structure to make that happen.
• Study full chip floorplan and come up with Network on Chip by considering different factors stemming from behavioral design to physical design.
• Write comprehensive documents spelling out details of one work and train other while moving on to another task.
• Manage and monitor changes in the given tasks are project matures and be quick on the feet to re-align with new or different requirements.
• Write and edit csh, perl, python or ruby scripts to automate work as needed.
• Research and document various pre silicon execution methods and thereby helping leads in assessing and coin new methodologies.

REQUIREMENTS:

• Solid fundamental understanding of Computer Architecture and Digital Design concepts.
• Strong background in STA, Clocks and Power optimization techniques.
• Experience with Verilog or SystemVerilog and UVM (preferred)
• Familiarity with scripting languages: perl or tcl or ruby or Bash or python, etc.
• Strong analytical skills and attention to detail.
• Excellent written and verbal communication skills.
• Ability to solve problems independently along with great teamwork skills

 GROWTH OPPORTUNITIES:

• Chip lead is a very visible and sought out role. In this position, individuals get to make various connections and learn a lot of different things through a project execution thereby making them ideal candidate to grow and taking other leadership roles.
• You will be exposed to various design, verification, test, synthesis, timing and physical design concepts.
• Exposure to Formal Verification Techniques.
• Be directly involved in the development of next-generation AI products.
• Develop communication skills further in a professional environment; meet and connect with industry experts and professionals.

ACADEMIC CREDENTIALS:

• Bachelors or master’s degree in Computer, Electrical, Mechatronics Engineering or Engineering Science or similar.

#LI-TB1

#LI-Hybrid

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE TEAM:

This team is a coveted team leading technical innovation and execution of cutting-edge AI technology both in inference and generative AI. AI Chip lead is responsible for creating micro architecture spec, enabling execution by understanding and removing design and implementation roadblocks, facilitating feature enablement, overall health of the project along with its timely execution. In this capacity, we interact with architecture, physical design, test, front end, design verification, project management, post-silicon bring-up and diagnostic teams, and occasionally software teams as well. We are responsible for analyzing past programs and inheriting best practices and improve upon them with current SOC requirements. While execution is our utmost priority, we do represent or participate in companywide discussion related to best execution strategies and methods.  

This team comprises of a few engineers who have extensive and varied experience in Design, Design for Test, Design Verification, Physical Design and Platform, to name a few among other disciplines of design process. We believe in growing engineers into successful leads and therefore credit in hiring young engineers and train them. This is a high visibility team and is well respected and recognized in the company.  Our core values are – Humility, Help and Hygiene.

THE ROLE:

There is no pre-requisite for you to have an RTL design background (as mentioned in the team introduction), you can be an AISC engineer with whatever background within hardware design execution realm and you can apply to this role. You will be responsible for creating micro architecture spec, refining flow for existing and new methodologies and initiatives. In some way you get to choose what you want to do in terms of your role and visibility. We expect you to have a lot of questions and therefore you must be self-driven to talk to other engineers, use AMD resources to find the answers. We also expect you to ask questions and engage in discussions (respectfully).  You will work with leading industry tools and design/verification/dfx/timing/power/physical design concepts to assist in developing the specification along with infrastructure flows to facilitate execution.

THE PERSON:

The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification, Design for Test, Synthesis, Static Timing Analysis, Power Verification and optimization, Physical Design aspects like Floorplan, Full chip timing, Place and Route and Utilization experiments.

While we do understand that it is very difficult to have knowledge on expected areas, the candidate should have strong foundation in digital design to pick up the necessary concepts and should strive to continuously learn on the job.

Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or any pre-silicon technical issue. Expertise in scripting(perl, tcl or python) is a must. You should be able strike a balance between collaborative problem-solving and independent solution development.   

KEY RESPONSIBILITIES:

• Study both high-level and micro architecture specifications and use Computer Architecture knowledge and background to gain an in depth understanding of new features or changes proposed in new projects.
• Automate (using scripting language) any execution flow that lacks efficiency or consumes more time to complete after discussing the overall picture and required data structure to make that happen.
• Study full chip floorplan and come up with Network on Chip by considering different factors stemming from behavioral design to physical design.
• Write comprehensive documents spelling out details of one work and train other while moving on to another task.
• Manage and monitor changes in the given tasks are project matures and be quick on the feet to re-align with new or different requirements.
• Write and edit csh, perl, python or ruby scripts to automate work as needed.
• Research and document various pre silicon execution methods and thereby helping leads in assessing and coin new methodologies.

REQUIREMENTS:

• Solid fundamental understanding of Computer Architecture and Digital Design concepts.
• Strong background in STA, Clocks and Power optimization techniques.
• Experience with Verilog or SystemVerilog and UVM (preferred)
• Familiarity with scripting languages: perl or tcl or ruby or Bash or python, etc.
• Strong analytical skills and attention to detail.
• Excellent written and verbal communication skills.
• Ability to solve problems independently along with great teamwork skills

 GROWTH OPPORTUNITIES:

• Chip lead is a very visible and sought out role. In this position, individuals get to make various connections and learn a lot of different things through a project execution thereby making them ideal candidate to grow and taking other leadership roles.
• You will be exposed to various design, verification, test, synthesis, timing and physical design concepts.
• Exposure to Formal Verification Techniques.
• Be directly involved in the development of next-generation AI products.
• Develop communication skills further in a professional environment; meet and connect with industry experts and professionals.

ACADEMIC CREDENTIALS:

• Bachelors or master’s degree in Computer, Electrical, Mechatronics Engineering or Engineering Science or similar.

#LI-TB1

#LI-Hybrid