Analog/Mixed Signal Design, Sr. Engineering Mgr

Jun 01, 2024
San Jose, United States
... Not specified
... Senior
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




 

THE ROLE:

Manage/Lead the MSIP design team to deliver on cost, per committed performance, and time-to-market goals.

 

THE PERSON:

Maintain a performance culture of excellence with a commitment to accountability, transparency, and to exceeding expectations – No surprise mindset. Embrace innovation and continuous learning to solve complex problems, seeking root causes and solutions to problems.

 

KEY RESPONSIBILITIES:

  • Hands on experience in analog/mixed signal (AMS) IP designs including DDR/Serdes PHY circuit, performance optimization and verification techniques and methodologies. Familiarity with mixed-signal and/or digital first top-down design methodologies.
  • Mixed signal IP (MSIP) design expertise and experiences including but not limited to the following, High speed custom digital/IO/Clocking design and tuning. Experiences in high-speed custom digital design for data and control paths is highly desirable.
  • Drive/own the plan to meet the committed IP objectives. Collaborate with peers and team leaders to prioritize near term execution imperatives and long-term strategic goals. Collaborate with cross-functional team such as layout, DFT, PnR, and verifications on all aspects of design convergence and QA activities.
  • Familiarity with MSIP integration workflows, requirements collaterals QA and handoff in complicated SOCs environment. Able to converse and interlock with SOC owners on IP collaterals technical requirements.
  • Collaborate with MSIP post-silicon validation & characterization (VnC) teams to put together and execute post-silicon VnC plan and sign-off on IP production readiness. Hands-on to Participate in debug and root-cause activities.
  • Adopt and deploy golden AMS design methodologies as part of execution plan and for ongoing improvements in IP development time and quality. enforce best in class design methodologies for the team.
  • Work with the greater AMD cross functional groups to integrate new capabilities into the MSIP design process.
  • Work directly, willing to be hands-on, and with project management team to Provide supervision of team activities, track and monitor project schedules, identify, and drive corrective actions and mitigations plans to meet plan goals, and ensure successful outcomes.

 

PREFERRED EXPERIENCE:

  • Hands on experience in high-speed SerDes/DDR PHY design
  • MSIP design team leadership and technical management. 
  • Proven record of delivering complicated high speed PHY designs on schedule and with best-in-class performance metrics.  
  • 10+ years’ experience managing and directing the development of commercially successful high speed PHY design team.
  • Self-motivated, disciplined, organized, and detailed orientated.  Able to drive independently to solve problems and to be collaborative with the global org/global AMD design community to identify optimum solutions to novel problems. Strike the right balance between the speed and quality of required decisions.
  • Strong communications skills combined with broad technical skills.  This is a highly visible role in which the team will look to you as the guide for leading execution and design activities on a day-to-day basis.

ACADEMIC CREDENTIALS:

MSEE or PhD and 15+ years of related professional experience.

 

LOCATION:

San Jose, CA

 

 

 

#LI-DD3
#LI-HYBRID




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

THE ROLE:

Manage/Lead the MSIP design team to deliver on cost, per committed performance, and time-to-market goals.

 

THE PERSON:

Maintain a performance culture of excellence with a commitment to accountability, transparency, and to exceeding expectations – No surprise mindset. Embrace innovation and continuous learning to solve complex problems, seeking root causes and solutions to problems.

 

KEY RESPONSIBILITIES:

  • Hands on experience in analog/mixed signal (AMS) IP designs including DDR/Serdes PHY circuit, performance optimization and verification techniques and methodologies. Familiarity with mixed-signal and/or digital first top-down design methodologies.
  • Mixed signal IP (MSIP) design expertise and experiences including but not limited to the following, High speed custom digital/IO/Clocking design and tuning. Experiences in high-speed custom digital design for data and control paths is highly desirable.
  • Drive/own the plan to meet the committed IP objectives. Collaborate with peers and team leaders to prioritize near term execution imperatives and long-term strategic goals. Collaborate with cross-functional team such as layout, DFT, PnR, and verifications on all aspects of design convergence and QA activities.
  • Familiarity with MSIP integration workflows, requirements collaterals QA and handoff in complicated SOCs environment. Able to converse and interlock with SOC owners on IP collaterals technical requirements.
  • Collaborate with MSIP post-silicon validation & characterization (VnC) teams to put together and execute post-silicon VnC plan and sign-off on IP production readiness. Hands-on to Participate in debug and root-cause activities.
  • Adopt and deploy golden AMS design methodologies as part of execution plan and for ongoing improvements in IP development time and quality. enforce best in class design methodologies for the team.
  • Work with the greater AMD cross functional groups to integrate new capabilities into the MSIP design process.
  • Work directly, willing to be hands-on, and with project management team to Provide supervision of team activities, track and monitor project schedules, identify, and drive corrective actions and mitigations plans to meet plan goals, and ensure successful outcomes.

 

PREFERRED EXPERIENCE:

  • Hands on experience in high-speed SerDes/DDR PHY design
  • MSIP design team leadership and technical management. 
  • Proven record of delivering complicated high speed PHY designs on schedule and with best-in-class performance metrics.  
  • 10+ years’ experience managing and directing the development of commercially successful high speed PHY design team.
  • Self-motivated, disciplined, organized, and detailed orientated.  Able to drive independently to solve problems and to be collaborative with the global org/global AMD design community to identify optimum solutions to novel problems. Strike the right balance between the speed and quality of required decisions.
  • Strong communications skills combined with broad technical skills.  This is a highly visible role in which the team will look to you as the guide for leading execution and design activities on a day-to-day basis.

ACADEMIC CREDENTIALS:

MSEE or PhD and 15+ years of related professional experience.

 

LOCATION:

San Jose, CA

 

 

 

#LI-DD3
#LI-HYBRID

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