ASIC Design and Test Engineer

Feb 16, 2024
Austin, United States
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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ASIC Design and Test Engineer

 

THE ROLE: 

The focus of this role is to drive and implement Design for Test architecture features and methods for next generation high end Graphics designs.

 

THE PERSON: 

You have a passion for modern, complex graphics processor architecture, digital design, verification, latest packaging technology. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

  • Coordinate test and quality requirements across SoC, IP and Product teams
  • Lead DFT design and STA optimizations to meet design Power/Performance and Area targets
  • Integrate scan control and test compression logic construction to achieve synthesis and physical design requirement
  • Participate in DRC, test generation and test pattern validation to achieve high test fault coverage targets
  • Construct and validate test vectors across multiple fault models and levels of design hierarchy
  • Drive pre and post silicon structural test debug across design, SoC and product teams
  • Interact with a multi-discipline Geo collocated team

 

PREFERRED EXPERIENCE: 

  • 7+ years of ASIC/Custom design and testability experience
  • Strong background and experience with Scan design, System and Test Clock architecture, ATPG methodology and commercial EDA tools, including:
  • Scan planning, insertion
  • Compression logic generation
  • Static timing analysis
  • Test constraints development
  • Test and pattern generation and validation w/wo timing annotation
  • Fault simulation
  • Strong understanding of test models: Stuck At, Transition, Cell Aware, Bridging, etc.
  • Fault analysis and diagnostic capabilities.
  • Solid understanding of scripting, Linux/Unix environment
  • Basic knowledge of logical and physical design (PD) processes
  • Strong organization, problem solving, and analytical skills are must
  • Results oriented, self-starter able to independently drive tasks to completion
  • Strong verbal and written communication skills  

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 



At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

ASIC Design and Test Engineer

 

THE ROLE: 

The focus of this role is to drive and implement Design for Test architecture features and methods for next generation high end Graphics designs.

 

THE PERSON: 

You have a passion for modern, complex graphics processor architecture, digital design, verification, latest packaging technology. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

  • Coordinate test and quality requirements across SoC, IP and Product teams
  • Lead DFT design and STA optimizations to meet design Power/Performance and Area targets
  • Integrate scan control and test compression logic construction to achieve synthesis and physical design requirement
  • Participate in DRC, test generation and test pattern validation to achieve high test fault coverage targets
  • Construct and validate test vectors across multiple fault models and levels of design hierarchy
  • Drive pre and post silicon structural test debug across design, SoC and product teams
  • Interact with a multi-discipline Geo collocated team

 

PREFERRED EXPERIENCE: 

  • 7+ years of ASIC/Custom design and testability experience
  • Strong background and experience with Scan design, System and Test Clock architecture, ATPG methodology and commercial EDA tools, including:
  • Scan planning, insertion
  • Compression logic generation
  • Static timing analysis
  • Test constraints development
  • Test and pattern generation and validation w/wo timing annotation
  • Fault simulation
  • Strong understanding of test models: Stuck At, Transition, Cell Aware, Bridging, etc.
  • Fault analysis and diagnostic capabilities.
  • Solid understanding of scripting, Linux/Unix environment
  • Basic knowledge of logical and physical design (PD) processes
  • Strong organization, problem solving, and analytical skills are must
  • Results oriented, self-starter able to independently drive tasks to completion
  • Strong verbal and written communication skills  

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 
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