ASIC Physical Design Engineer-GPU

Sep 10, 2022
Santa Clara, United States
... Not specified
... Intermediate
Full time
... Office work


What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

The Role:

This is a great opportunity to be part of the next generation GPU chip development team at AMD Santa Clara for ASIC Physical Design engineer. You will join us as Sr. Staff Engineer / Principal Member of Technical Staff.

 

KEY RESPONSIBILITIES:

 

  • Senior level lead engineer driving PPA improvements in both pre-silicon and post-silicon design phase
  • Drive cross-functional teams (technology, CAD tools, platform characterization , binning  practices and design methodology) and optimize margining practices across boundaries to deliver best in class performance/watt
  • Improve low voltage margining methodology and design practices to improve Vmin and performance/watt for low power GFXIP
  • Drive design practices to improve boost frequency for GFXIP
  • Drive silicon correlation and deliver systematic improvements to improve silicon to STA on high performance Graphics IP

 

PREFERRED EXPERIENCE:

 

  • Over 18 years’ experience with BSEE/BSCS or 15+ years of MSEE or MSCE in ASIC Physical Design from RTL to GDSII
  • Excellent analytical and problem-solving skills along with attention to details
  • Strong RTL analysis skills including Verilog, Timing Analysis and library understanding
  • Strong knowledge in design margining methodology, low voltage design, silicon – STA correlation
  • Hands on experience in taping out 5nm, 7nm, 14nm and/or 16nm SOC
  • Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
  • Strong communication, Time Management, and Presentation Skills
  • Must be a self-starter, and be able to independently and efficiently drive tasks to completion
  • Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player

 

ACADEMIC CREDENTIALS

 

Bachelor's or Master's Degree in Electrical Engineering, Computer Science, or equivalent is preferred. 

#LI-DC3

 

 

 


Requisition Number: 181184 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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