Cache Verification Design Engineer
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AMD’s Cores Organization delivers industry leading CPU’s and caches that are the foundation of AMD’s server, client, and gaming business. We are looking for a microprocessor verification engineer to join this innovative team as a technical contributor. They will build their expertise as they help the team deliver cutting-edge designs in a dynamic environment. The candidate will join the team based in Fort Collins, CO.
The candidate should have strong analytical thinking and problem-solving skills with excellent attention to details. We work on programs with long timelines, so self-motivation and a commitment to meeting deadlines is required. We are pushing the envelope on chip performance, so the status quo must be challenged on every program. This requires creativity and innovation, but also excellent verbal and written communication skills. We work in small teams, but we are part of a large cross-site Core’s organization, so teamwork is also vital our success.
- Perform functional verification of high-speed Microprocessor designs, including development of infrastructure, directed and random test suites at behavioral RTL and gate design levels across SoC, Core and block hierarchies.
- Develop environments, infrastructure, and test plans to accommodate both full chip and stand-alone block-level verification and debug capabilities using simulation tools, debug tools and programming skills, based on in-depth understanding of the architecture and HDL/logical design of the microprocessor.
- Work with RTL design team to define verification strategy for our CPU cores, caches, and system interfaces
- Participate in development of formal verification techniques.
- Measure and analyze coverage terms, address exposed weaknesses to meet design/project quality objectives.
- Programming proficiency in x86 assembly, C/C++, and Ruby languages or similar.
- Understanding of modern computer architecture, especially cache design and out of order execution
- Experience with Verilog HDL and System Verilog.
- Knowledge of verification techniques of microprocessors/ASIC designs
- BS/MS in EE, CS, CSE (or similar)
Fort Collins, Colorado, USA
COMPENSATION RANGE & BENEFITS:
Expected to range from $78,890.00 to $112,700.00, commensurate with experience and specific skill sets. Benefits offered are described here.
Requisition Number: 183341
Country: United States State: Colorado City: Ft Collins
Job Function: Design
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