CPU POWER MANAGEMENT RTL/ARCHITECTURE ENGINEER

Mar 28, 2024
Santa Clara, Cuba
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




 

 

Do you want to be at the forefront of designing the next Ryzen, Threadripper or Epyc CPU? AMD is seeking an experienced and creative processor designer to develop microarchitecture for the CPU core clocking, reset, and power management IP used in our next-generation processor.

 

You are experienced in the power management aspect of IP development processes and have a consistent track record of delivering timely, high-quality products. A broad and thorough understanding of microprocessor architecture and design is required.

 

KEY RESPONSIBILITIES:

  • Develop and design microarchitecture for core clocking, reset, and power management IPs for next-generation processors.
  • Collaborate with architecture, design verification, and physical design teams to ensure the successful integration of IPs into the an overall processor design using cutting-edge fabrication technology.
  • Create detailed specifications and documentation for the microarchitecture of the IPs.
  • Implement RTL designs in Verilog/SystemVerilog, ensuring optimization for timing, area, power, and performance.
  • Develop firmware code in C/C++ for IP initialization, configuration, and control, emphasizing functionality.
  • Collaborate with firmware engineers to ensure seamless integration of RTL designs with firmware functionalities.
  • Conduct RTL linting, clock domain crossing (CDC) analysis, and other relevant checks to ensure design correctness.
  • Work closely with verification engineers to develop comprehensive test plans and ensure the functional correctness of RTL designs.
  • Debug RTL and firmware issues and collaborate with cross-functional teams to resolve them.
  • Participate in design reviews, providing valuable insights and feedback to improve design quality and efficiency.

PREFERRED EXPERIENCE:

  • Proven track record C/C++ development, including but not limited to embedded firmware, especially firmware controlling power management functionalities.
  • Prior engagement in successful projects related to clocking, reset, and power management IPs would be highly beneficial.
  • Experience in RTL design and microarchitecture development for complex IPs or processors
  • Proficiency in Verilog/SystemVerilog for RTL design and verification.
  • Experience in developing firmware in C/C++ for power management, clocking, and reset functionalities is highly desirable.
  • Strong understanding of digital design fundamentals, including synchronous and asynchronous design techniques, clock domain crossing, multi-voltage design, and power-aware design.
  • Knowledge of low-power design methodologies and power management techniques such as clock gating, power gating, and dynamic voltage and frequency scaling (DVFS).
  • Excellent problem-solving skills and the ability to debug complex RTL & firmware issues.
  • Strong communication and teamwork skills, with the ability to collaborate effectively with cross-functional teams.
  • Familiarity with firmware development tools, such as compilers, debuggers, and IDEs.
  • Understanding of firmware-hardware interactions and experience in firmware-hardware co-verification and validation.
  • Ability to analyze firmware performance and optimize code for efficiency and resource utilization.

ADVANTAGEOUS SKILLS:

  • Experience with Design for Debug (DFD) methodologies, including incorporating debug features into designs for efficient post-silicon debugging.
  • Familiarity with Design for Test (DFT) techniques and methodologies to enhance the testability of hardware components.
  • Familiarity with clock distribution networks, PLLs (Phase-Locked Loops), and clock tree synthesis is an added advantage.

ACADEMIC CREDENTIALS:

  • MS in EE, ECE, Comp Eng or Comp Sci plus industry experience in RTL design and microarchitecture development for processors or complex IPs.

 

LOCATION:

  • Santa Clara, CA USA

 

#LI-AJ1

 




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

 

Do you want to be at the forefront of designing the next Ryzen, Threadripper or Epyc CPU? AMD is seeking an experienced and creative processor designer to develop microarchitecture for the CPU core clocking, reset, and power management IP used in our next-generation processor.

 

You are experienced in the power management aspect of IP development processes and have a consistent track record of delivering timely, high-quality products. A broad and thorough understanding of microprocessor architecture and design is required.

 

KEY RESPONSIBILITIES:

  • Develop and design microarchitecture for core clocking, reset, and power management IPs for next-generation processors.
  • Collaborate with architecture, design verification, and physical design teams to ensure the successful integration of IPs into the an overall processor design using cutting-edge fabrication technology.
  • Create detailed specifications and documentation for the microarchitecture of the IPs.
  • Implement RTL designs in Verilog/SystemVerilog, ensuring optimization for timing, area, power, and performance.
  • Develop firmware code in C/C++ for IP initialization, configuration, and control, emphasizing functionality.
  • Collaborate with firmware engineers to ensure seamless integration of RTL designs with firmware functionalities.
  • Conduct RTL linting, clock domain crossing (CDC) analysis, and other relevant checks to ensure design correctness.
  • Work closely with verification engineers to develop comprehensive test plans and ensure the functional correctness of RTL designs.
  • Debug RTL and firmware issues and collaborate with cross-functional teams to resolve them.
  • Participate in design reviews, providing valuable insights and feedback to improve design quality and efficiency.

PREFERRED EXPERIENCE:

  • Proven track record C/C++ development, including but not limited to embedded firmware, especially firmware controlling power management functionalities.
  • Prior engagement in successful projects related to clocking, reset, and power management IPs would be highly beneficial.
  • Experience in RTL design and microarchitecture development for complex IPs or processors
  • Proficiency in Verilog/SystemVerilog for RTL design and verification.
  • Experience in developing firmware in C/C++ for power management, clocking, and reset functionalities is highly desirable.
  • Strong understanding of digital design fundamentals, including synchronous and asynchronous design techniques, clock domain crossing, multi-voltage design, and power-aware design.
  • Knowledge of low-power design methodologies and power management techniques such as clock gating, power gating, and dynamic voltage and frequency scaling (DVFS).
  • Excellent problem-solving skills and the ability to debug complex RTL & firmware issues.
  • Strong communication and teamwork skills, with the ability to collaborate effectively with cross-functional teams.
  • Familiarity with firmware development tools, such as compilers, debuggers, and IDEs.
  • Understanding of firmware-hardware interactions and experience in firmware-hardware co-verification and validation.
  • Ability to analyze firmware performance and optimize code for efficiency and resource utilization.

ADVANTAGEOUS SKILLS:

  • Experience with Design for Debug (DFD) methodologies, including incorporating debug features into designs for efficient post-silicon debugging.
  • Familiarity with Design for Test (DFT) techniques and methodologies to enhance the testability of hardware components.
  • Familiarity with clock distribution networks, PLLs (Phase-Locked Loops), and clock tree synthesis is an added advantage.

ACADEMIC CREDENTIALS:

  • MS in EE, ECE, Comp Eng or Comp Sci plus industry experience in RTL design and microarchitecture development for processors or complex IPs.

 

LOCATION:

  • Santa Clara, CA USA

 

#LI-AJ1

 

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