Data Fabric Front-End Physical Design Engineer

Mar 28, 2024
Austin, United States
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE:

This is a front-end design engineering position on AMD’s Data Fabric IP. The Data Fabric is the high-bandwidth, high performance, fabric network logic that ties together all the IPs on an SOC. Every product that AMD sells has its own custom-designed Data Fabric, so this role gives an engineer the opportunity to work on a broad array of products that address a variety of markets, including traditional servers, high performance computing, client desktop and laptop PCs, machine intelligence, graphics, console gaming, embedded, and customer-specific applications. It is a challenging position that involves working at a fast pace of innovation on the cutting edge of technology. Come join the AMD team!

 

THE PERSON:

The candidate should be able to work cooperatively with a talented global team and use his or her engineering skills to solve novel problems and optimize designs and flows.

 

KEY RESPONSIBILITIES:

  • Work with the Data Fabric architects and the chip floorplanning team to develop a custom Data Fabric topology

  • Synthesize Data Fabric IP using Synopsys tools and work with the micro-architects to ensure the design components meet the project’s area, power, and performance goals

  • Provide feedback to RTL team to resolve timing, power, area, LINT, DFT, and cross-clock-domain issues.

  • Provide interface to integrate IP blocks into the SOC and resolve the same types of power, timing, area, and formal equivalence checking at the chip level.

  • Analyze design power and devise improvements through architectural or flow optimizations

PREFERRED EXPERIENCE:

  • Extensive working knowledge, gained through multiple tapeouts, of the latest generation of Synopsys design tools, including Design Compiler NXT, Formality, Power Compiler, PrimeTime, Fusion Compiler, and IC Compiler II
  • A proven understanding of computer architecture 
  • Knowledge of high performance interconnection logic and networks is a plus

ACADEMIC CREDENTIALS:

  • MS degree in Computer Engineering preferred

LOCATION:

Austin, TX 

 

#LI-CS1




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

This is a front-end design engineering position on AMD’s Data Fabric IP. The Data Fabric is the high-bandwidth, high performance, fabric network logic that ties together all the IPs on an SOC. Every product that AMD sells has its own custom-designed Data Fabric, so this role gives an engineer the opportunity to work on a broad array of products that address a variety of markets, including traditional servers, high performance computing, client desktop and laptop PCs, machine intelligence, graphics, console gaming, embedded, and customer-specific applications. It is a challenging position that involves working at a fast pace of innovation on the cutting edge of technology. Come join the AMD team!

 

THE PERSON:

The candidate should be able to work cooperatively with a talented global team and use his or her engineering skills to solve novel problems and optimize designs and flows.

 

KEY RESPONSIBILITIES:

  • Work with the Data Fabric architects and the chip floorplanning team to develop a custom Data Fabric topology

  • Synthesize Data Fabric IP using Synopsys tools and work with the micro-architects to ensure the design components meet the project’s area, power, and performance goals

  • Provide feedback to RTL team to resolve timing, power, area, LINT, DFT, and cross-clock-domain issues.

  • Provide interface to integrate IP blocks into the SOC and resolve the same types of power, timing, area, and formal equivalence checking at the chip level.

  • Analyze design power and devise improvements through architectural or flow optimizations

PREFERRED EXPERIENCE:

  • Extensive working knowledge, gained through multiple tapeouts, of the latest generation of Synopsys design tools, including Design Compiler NXT, Formality, Power Compiler, PrimeTime, Fusion Compiler, and IC Compiler II
  • A proven understanding of computer architecture 
  • Knowledge of high performance interconnection logic and networks is a plus

ACADEMIC CREDENTIALS:

  • MS degree in Computer Engineering preferred

LOCATION:

Austin, TX 

 

#LI-CS1

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