DDR Director

Mar 10, 2023
Austin, United States
... Not specified
... Senior
Full time
... Office work

WHAT YOU DO AT AMD CHANGES EVERYTHING

 

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

 

AMD together we advance_

THE ROLE: 

As a member of the IO and Circuit Technologies Group, you will help bring to life cutting-edge designs. As a member of the High-Speed IO Interface IP engineering team, you will lead a Memory sub-team working  closely with Architecture, IP design, Physical Design, SoC, Platform, Product and other engineering teams to productize best-in-class DDR/LPDDR PHY IP on silicon.

THE PERSON:

A successful candidate will work with senior silicon design engineers and leaders. The candidate will be highly technical and detail-oriented, possessing excellent leadership, communication and problem-solving skills.

KEY RESPONSIBLITIES:

  • Provide systems engineering and post-silicon support for DDR/LPDDR Memory interface IP 
    • New product bring-up support from first-silicon in the lab through initial production 
    • Triage observations from silicon validation, and help debug issues with ATE, Platform, Firmware, and Characterization / Compliance teams 
  • Provide expertise and support in silicon design, process and integration flows for Memory Interface IP 
    • Pre-Silicon engagement with internal and external PHY design teams, Platform, ATE, IP design, and Firmware teams 
  • Perform analog circuit and mixed-signal design/analysis for high-speed I/O and Memory Interface IP in advanced process technologies.

 

PREFERRED EXPERIENCE:

  • Bachelor's or Graduate degree in Electrical Engineering or related discipline, with relevant professional experience, expertise, and leadership in applicable DDR/LPDDR Memory Interface PHY IP
  • Professional experience and leadership in the semiconductor industry doing analog mixed-signal circuit design, test and debug 
  • High-speed I/O design experience, including strong understanding of Tx, Rx, PLL/DLL, Clocking, Equalization, VREG techniques and circuits, Training algorithms and Firmware 
  • Experience with advanced FinFET semiconductor technologies such as 7nm and finer geometries preferable 
  • Basic understanding of Verilog RTL, digital circuits, as well as a general knowledge and experience of the backend physical flow 
  • Familiarity with the range of design areas and tools, (HSPICE, PrimeTime, etc.) and understanding of design/technology interactions 
  • Python and/or Perl programming for test scripts, data analysis, etc. Should be familiar with UNIX and Windows environment 
  • Laboratory experience, including hands-on use of equipment: Oscilloscopes, Signal generators, BERT, Logic analyzers, etc. 
  • Strong analytical and problem solving skills involving post-silicon debug and pre-silicon issues 
  • Good teamwork and communication skills to interact with a broad range of teams are mandatory.

 

ACADEMIC CREDENTIALS:

  • Electrical Engineering: BS / MS / PhD with relevant exp. including in a technical leadership role 

 

#LI-DC1

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

As a member of the IO and Circuit Technologies Group, you will help bring to life cutting-edge designs. As a member of the High-Speed IO Interface IP engineering team, you will lead a Memory sub-team working  closely with Architecture, IP design, Physical Design, SoC, Platform, Product and other engineering teams to productize best-in-class DDR/LPDDR PHY IP on silicon.

THE PERSON:

A successful candidate will work with senior silicon design engineers and leaders. The candidate will be highly technical and detail-oriented, possessing excellent leadership, communication and problem-solving skills.

KEY RESPONSIBLITIES:

  • Provide systems engineering and post-silicon support for DDR/LPDDR Memory interface IP 
    • New product bring-up support from first-silicon in the lab through initial production 
    • Triage observations from silicon validation, and help debug issues with ATE, Platform, Firmware, and Characterization / Compliance teams 
  • Provide expertise and support in silicon design, process and integration flows for Memory Interface IP 
    • Pre-Silicon engagement with internal and external PHY design teams, Platform, ATE, IP design, and Firmware teams 
  • Perform analog circuit and mixed-signal design/analysis for high-speed I/O and Memory Interface IP in advanced process technologies.

 

PREFERRED EXPERIENCE:

  • Bachelor's or Graduate degree in Electrical Engineering or related discipline, with relevant professional experience, expertise, and leadership in applicable DDR/LPDDR Memory Interface PHY IP
  • Professional experience and leadership in the semiconductor industry doing analog mixed-signal circuit design, test and debug 
  • High-speed I/O design experience, including strong understanding of Tx, Rx, PLL/DLL, Clocking, Equalization, VREG techniques and circuits, Training algorithms and Firmware 
  • Experience with advanced FinFET semiconductor technologies such as 7nm and finer geometries preferable 
  • Basic understanding of Verilog RTL, digital circuits, as well as a general knowledge and experience of the backend physical flow 
  • Familiarity with the range of design areas and tools, (HSPICE, PrimeTime, etc.) and understanding of design/technology interactions 
  • Python and/or Perl programming for test scripts, data analysis, etc. Should be familiar with UNIX and Windows environment 
  • Laboratory experience, including hands-on use of equipment: Oscilloscopes, Signal generators, BERT, Logic analyzers, etc. 
  • Strong analytical and problem solving skills involving post-silicon debug and pre-silicon issues 
  • Good teamwork and communication skills to interact with a broad range of teams are mandatory.

 

ACADEMIC CREDENTIALS:

  • Electrical Engineering: BS / MS / PhD with relevant exp. including in a technical leadership role 

 

#LI-DC1

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