DDR PHY Analog Design Engineer

Apr 02, 2024
Boston, United States
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




 

THE ROLE :
The candidate will be a member of the Memory I/O design team leading and supporting the definition, specification, system simulation and implementation of future DDR,LPDDR IPs. The focus of the activity will be centered around the circuit architecture and working with the team leading the design of critical high-speed analog and digital blocks, definition of specifications for the high speed data path; definition of algorithms for calibration,  equalization; and development of abstracted models for link performance simulations.

 

THE PERSON:

Leadership qualities with ability to guide multiple engineers to create successful high quality analog circuits.

Will have analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation

Strong/effective communication skills

Enthusiastic team-first mentality

 

RESPONSIBILITIES:

  • Contribute to the definition of circuit architecture and to lead the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for DDR,LPDDR PHYs
  • Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
  • Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.
  • Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
  • Participate and contribute to the definition of development flows that improve efficiency and quality of execution  

 

PREFERRED EXPERIENCE. 

  •  A proven successful track record in leading Analog Design for High Speed IOs in multiple projects.
  • Clear understanding of design trade-offs related to Circuits, Timing, Architecture and System design.
  • Solid hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
  • Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
  • Advanced knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
  • Expert to dig into RTL or FW code supporting the custom circuit implementation

 

ACADEMIC CREDENTIALS:

Masters or PHD in Electrical or Computer Engineering

 

LOCATION- Boxborough, MA 

 

#LI-SL3

 




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

THE ROLE :
The candidate will be a member of the Memory I/O design team leading and supporting the definition, specification, system simulation and implementation of future DDR,LPDDR IPs. The focus of the activity will be centered around the circuit architecture and working with the team leading the design of critical high-speed analog and digital blocks, definition of specifications for the high speed data path; definition of algorithms for calibration,  equalization; and development of abstracted models for link performance simulations.

 

THE PERSON:

Leadership qualities with ability to guide multiple engineers to create successful high quality analog circuits.

Will have analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation

Strong/effective communication skills

Enthusiastic team-first mentality

 

RESPONSIBILITIES:

  • Contribute to the definition of circuit architecture and to lead the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for DDR,LPDDR PHYs
  • Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
  • Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.
  • Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
  • Participate and contribute to the definition of development flows that improve efficiency and quality of execution  

 

PREFERRED EXPERIENCE. 

  •  A proven successful track record in leading Analog Design for High Speed IOs in multiple projects.
  • Clear understanding of design trade-offs related to Circuits, Timing, Architecture and System design.
  • Solid hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
  • Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
  • Advanced knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
  • Expert to dig into RTL or FW code supporting the custom circuit implementation

 

ACADEMIC CREDENTIALS:

Masters or PHD in Electrical or Computer Engineering

 

LOCATION- Boxborough, MA 

 

#LI-SL3

 

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