DDRPHY AMS Lead Engineer
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Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
DDRPHY AMS Lead Engineer
The Role : The candidate will be a Lead Member of the Memory I/O design team supporting the definition, specification, system simulation and implementation of future DDR,LPDDR,GDDR IPs. The focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of specifications for the high speed data path; definition of algorithms for calibration, equalization; and development of abstracted models for link performance simulations.
The Person :
- Will have analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation
- Strong/effective communication skills
- Enthusiastic team-first mentality
- Contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for DDR,LPDDR,GDDR PHYs
- Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
- Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.
- Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
- Participate and contribute to the definition of development flows that improve efficiency and quality of execution
- Lead design liaison for post Silicon characterization and productization/volume production efforts
Preferred Skilled Sets :
- A proven successful track record in circuit-architecture and modeling for High Speed IOs
- Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
- Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
- Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
- Ability to dig into RTL or FW code supporting the custom circuit implementation
- Masters or PHD in Electrical or Computer Engineering
Requisition Number: 164923
Country: United States State: Massachusetts City: Boxborough
Job Function: Design
Benefits offered are described here.
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