Design Integration Engineer

Apr 06, 2024
Cork, Ireland
... Not specified
... Intermediate
Full time
... Office work


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DESIGN INTEGRATION ENGINEER 

 

The AMD SerDes engineering team in Ireland are hiring for a passionate MTS level Integration Engineer to contribute to the development of complex mixed-signal SerDes designs in the latest CMOS FinFET processes. The role requires a focus on macro-level integration. High quality macro release processes contribute to robust silicon designs with seamless ingeration at the design toplevel for efficient tapeout of complex SoC.The successful candidate will work closely with an experienced mixed signal design team delivering world-class SerDes solutions.

  

Day to day responsibilities:  

  • Coordinate with all macro-level design owners to support high quality IP releases to enable SoC integration
  • Running and debugging the macro release flows
  • Running toplevel sign-off checks such as EMIR
  • Database / Library / Diskspace management
  • Coordinatation with with AMD CAD and Foundry Technology teams resolve macro-level release flow issues
  • As a key part of integration, you will also handle Project level on-boarding as well as SOC IP delivery / tape-out QA
  • Coordiation and schedule alignment across cross-functional team working on toplevel IP releases  

Preferred Experience:  

  • Prior experience in analog design and running EMIR flows
  • Prior ESD experience and exposure debugging CAD flows and reading log files will be an advantage
  • Strong interpersonal and organizational skills to collaborate with stakeholders from different departments
  • Experience in using industry standard circuit design and layout tools
  • Familiarity with Unix operatinc system and experience in scripting
  • Exposure to modern ASIC design methodologies and flows
  • "Tape-out” experience in advanced foundry process technologies
  • Excellent written and oral communication skills

  

Academic Credentials:  

Bachelors Degree or Masters Degree




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

DESIGN INTEGRATION ENGINEER 

 

The AMD SerDes engineering team in Ireland are hiring for a passionate MTS level Integration Engineer to contribute to the development of complex mixed-signal SerDes designs in the latest CMOS FinFET processes. The role requires a focus on macro-level integration. High quality macro release processes contribute to robust silicon designs with seamless ingeration at the design toplevel for efficient tapeout of complex SoC.The successful candidate will work closely with an experienced mixed signal design team delivering world-class SerDes solutions.

  

Day to day responsibilities:  

  • Coordinate with all macro-level design owners to support high quality IP releases to enable SoC integration
  • Running and debugging the macro release flows
  • Running toplevel sign-off checks such as EMIR
  • Database / Library / Diskspace management
  • Coordinatation with with AMD CAD and Foundry Technology teams resolve macro-level release flow issues
  • As a key part of integration, you will also handle Project level on-boarding as well as SOC IP delivery / tape-out QA
  • Coordiation and schedule alignment across cross-functional team working on toplevel IP releases  

Preferred Experience:  

  • Prior experience in analog design and running EMIR flows
  • Prior ESD experience and exposure debugging CAD flows and reading log files will be an advantage
  • Strong interpersonal and organizational skills to collaborate with stakeholders from different departments
  • Experience in using industry standard circuit design and layout tools
  • Familiarity with Unix operatinc system and experience in scripting
  • Exposure to modern ASIC design methodologies and flows
  • "Tape-out” experience in advanced foundry process technologies
  • Excellent written and oral communication skills

  

Academic Credentials:  

Bachelors Degree or Masters Degree

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