Design Verification Engineer

Apr 04, 2024
Cork, Ireland
... Not specified
... Intermediate
Full time
... Office work


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DESIGN VERIFICATION ENGINEER 

 

The AMD SerDes team in Ireland are hiring for a design  verification engineer to contribute to the pre-silicon verification of  complex mixed-signal ICs in the latest CMOS FinFET processes. The scope of the work is wide ranging including the verification of designs at the block level and system level to maximise pre-silicon tapeout coverage The successful candidate will work with an experienced cross functional design team delivering world-class SerDes solutions.

 

Day to day responsibilities:  

  • Verification Planning: Collaborate with design, architecture, and verification teams to develop comprehensive verification plans, defining verification strategies, goals, and methodologies to ensure thorough  coverage of functional requirements.
  • Testbench Development: Design and implement advanced verification environments and testbenches using industry-standard methodologies such as UVM (Universal Verification Methodology), and SystemVerilog.
  • Testcase Development: Create and execute testcases to verify the functionality, performance, and robustness of complex semiconductor designs, ensuring compliance with architectural specifications and industry standards.
  • Debugging and Analysis: Identify, isolate, and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams.
  • Verification Closure: Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.
  • Methodology Enhancement: Drive the adoption and evolution of verification methodologies, AI initiatives, tools, and best practices, continuously seeking opportunities to improve efficiency, scalability, and quality.
  • Documentation and Reporting: Generate clear and concise documentation, reports, and presentations to communicate verification results, status, and recommendations to stakeholders and management.

 

PREFERRED EXPERIENCE: 

  • 7+ years of experience in ASIC or SoC design verification, with a strong understanding of verification methodologies, techniques, and tools.
  • Proficiency in verification languages and methodologies such as SystemVerilog, and UVM.
  • Experience with scripting languages (e.g., Python, Perl, TCL) for testbench automation and data analysis.
  • Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues.
  • Excellent communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams and stakeholders.
  • Ability to thrive in a fast-paced, dynamic environment with a passion for innovation and continuous learning.

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

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Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

DESIGN VERIFICATION ENGINEER 

 

The AMD SerDes team in Ireland are hiring for a design  verification engineer to contribute to the pre-silicon verification of  complex mixed-signal ICs in the latest CMOS FinFET processes. The scope of the work is wide ranging including the verification of designs at the block level and system level to maximise pre-silicon tapeout coverage The successful candidate will work with an experienced cross functional design team delivering world-class SerDes solutions.

 

Day to day responsibilities:  

  • Verification Planning: Collaborate with design, architecture, and verification teams to develop comprehensive verification plans, defining verification strategies, goals, and methodologies to ensure thorough  coverage of functional requirements.
  • Testbench Development: Design and implement advanced verification environments and testbenches using industry-standard methodologies such as UVM (Universal Verification Methodology), and SystemVerilog.
  • Testcase Development: Create and execute testcases to verify the functionality, performance, and robustness of complex semiconductor designs, ensuring compliance with architectural specifications and industry standards.
  • Debugging and Analysis: Identify, isolate, and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams.
  • Verification Closure: Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.
  • Methodology Enhancement: Drive the adoption and evolution of verification methodologies, AI initiatives, tools, and best practices, continuously seeking opportunities to improve efficiency, scalability, and quality.
  • Documentation and Reporting: Generate clear and concise documentation, reports, and presentations to communicate verification results, status, and recommendations to stakeholders and management.

 

PREFERRED EXPERIENCE: 

  • 7+ years of experience in ASIC or SoC design verification, with a strong understanding of verification methodologies, techniques, and tools.
  • Proficiency in verification languages and methodologies such as SystemVerilog, and UVM.
  • Experience with scripting languages (e.g., Python, Perl, TCL) for testbench automation and data analysis.
  • Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues.
  • Excellent communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams and stakeholders.
  • Ability to thrive in a fast-paced, dynamic environment with a passion for innovation and continuous learning.

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

#LI-TT1
#LI-HYBRID

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