WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 
We are looking for an adaptive, self-motivated design verification engineer to join the AMD xGMI IP Verification Team. The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology. We are looking for dynamic candidates with excellent communication skills. The role also provides opportunity to work on various aspects of verification such as performance verification besides functional verification.

THE PERSON: 
We are looking for a passionate candidate to work on the state-of-the-art products with leading verification methodology. Take your current verification expertise and apply that to state of the are data center products involving complex protocols like PCIE, High Speed Interconnects, Encryptions, networking etc. We are looking for team players with good communication skills and experience collaborating with other engineers located in different sites/time zones.

KEY RESPONSIBILITIES: 

• Create IP level verification plan and test plans
• Coordinate with the subsystem teams for the test plan of the IP
• Develop IP level UVM test bench including the RAL/UVCs/Top Environment
• Work with the DV Architecture on a new UVM test-bench with CRV support
• Work with Designers on coverage closure including function coverage and code coverage
• Work on the test development for data encryption and decryption on transaction level
• Performance verification with the latency and bandwidth checking
• Coordinate with formal verification 
• Test support for emulation team
• Work with the global team to release the IP

PREFERRED EXPERIENCE:

• Experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
• Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and functional coverage with design team
• Good understanding of object-oriented programming concepts
• Experience with PCIE, High Speed Interconnect Protocol
• Verifying is system/sub system level involving multiple blocks
• Experience with protocols such as AXI, APB, AHB etc.
• Programming in scripting languages like Python, TCL, and Perl
• Familiarity with EDA tools for simulation, debugging, coverage analysis
• Exposure to formal verification methodologies
• System level understanding of PCIE based systems
• Integrating Verification IPs (VIP) & UVC in verification environment
• Experience in bringing up gate level simulation and debugging issues

ACADEMIC CREDENTIALS:

• PhD, master’s, or bachelor’s degree in electrical engineering or computer Engineering or related equivalent

LOCATION:

• Markham, Ontario, CA

#LI-DP1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 
We are looking for an adaptive, self-motivated design verification engineer to join the AMD xGMI IP Verification Team. The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology. We are looking for dynamic candidates with excellent communication skills. The role also provides opportunity to work on various aspects of verification such as performance verification besides functional verification.

THE PERSON: 
We are looking for a passionate candidate to work on the state-of-the-art products with leading verification methodology. Take your current verification expertise and apply that to state of the are data center products involving complex protocols like PCIE, High Speed Interconnects, Encryptions, networking etc. We are looking for team players with good communication skills and experience collaborating with other engineers located in different sites/time zones.

KEY RESPONSIBILITIES: 

• Create IP level verification plan and test plans
• Coordinate with the subsystem teams for the test plan of the IP
• Develop IP level UVM test bench including the RAL/UVCs/Top Environment
• Work with the DV Architecture on a new UVM test-bench with CRV support
• Work with Designers on coverage closure including function coverage and code coverage
• Work on the test development for data encryption and decryption on transaction level
• Performance verification with the latency and bandwidth checking
• Coordinate with formal verification 
• Test support for emulation team
• Work with the global team to release the IP

PREFERRED EXPERIENCE:

• Experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
• Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and functional coverage with design team
• Good understanding of object-oriented programming concepts
• Experience with PCIE, High Speed Interconnect Protocol
• Verifying is system/sub system level involving multiple blocks
• Experience with protocols such as AXI, APB, AHB etc.
• Programming in scripting languages like Python, TCL, and Perl
• Familiarity with EDA tools for simulation, debugging, coverage analysis
• Exposure to formal verification methodologies
• System level understanding of PCIE based systems
• Integrating Verification IPs (VIP) & UVC in verification environment
• Experience in bringing up gate level simulation and debugging issues

ACADEMIC CREDENTIALS:

• PhD, master’s, or bachelor’s degree in electrical engineering or computer Engineering or related equivalent

LOCATION:

• Markham, Ontario, CA

#LI-DP1