WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

DESIGN VERIFICATION METHODOLOGY SENIOR ENGINEER

THE ROLE: 

We are looking for an experienced design verification professional to take on the role of DV methodology, infrastructure and automation within the NBIO organization. She/He will be part of a team responsible for developing a scalable DV flow with emphasis on automation, architecture, power and performance. The qualified candidate will work closely with multiple teams and groups on charting verification strategy, automating the verification flow, defining the test bench architecture, and evaluating/deploying new DV methodologies and solutions with the goal of enabling the scalable IP DV strategy and infrastructure needed to support AMD’s aggressive product roadmap. 

THE PERSON: 

• Creative and innovative thinker who loves technical problems.
• Organized, enthusiastic and self-motivated with a strong interest in verification methodologies and automation.
• Be a self-starter, pro-active, and take ownership to drive tasks to completion.
• Excellent communication skills (verbal and written) with strong problem-solving, and attention to detail.
• Ability to work in a multi-discipline team and global setting as a solution enabler.

KEY RESPONSIBILITIES: 

• Work with system/design/DV architects on defining various aspects of the overall IP verification strategy and methodology.
• Identify, develop, and deploy design/DV flow, infrastructure, and automation enhancements.
• Develop and/or enhance in-house tools to improve productivity, metric collection, and tracking.
• Identify performance and productivity bottlenecks and come up with innovative solutions.
• Drive technical initiatives to improve AMD’s capabilities in IP validation/verification, including tool and script development, technical and procedural methodology improvement, and various other internal and cross-functional technical initiatives.
• Architect and develop testbench components as well as test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology.
• Adapt UVM testbenches and DV flows to support emulation and post-silicon activities.
• Evaluate and deploy the latest verification solutions, tools, and methodologies. 

PREFERRED SKILL SET & EXPERIENCE: 

• Senior experience in the ASIC industry including a design verification lead or DV architecture role.
• Deep knowledge of DV infrastructure, Make flow and other automation flows, shell, perl, python, ruby.
• Proficiency in Verilog, SystemVerilog, and C/C++.
• Extensive experience verifying complex designs using UVM, OVM or VMM.
• Expertise in constrained random verification methodologies, metric/coverage driven verification and formal verification.
• Exposure to emulation/HW acceleration for design verification, architectural prototyping, and virtual platforms for SW enablement.
• Familiarity with Jenkins, JIRA, JAMA, GIT, Perforce.
• Familiarity with industry standard high-speed protocols such as PCIe, SATA, USB.
• Experience with verification of Hardware-Firmware interaction is highly desirable.
• Familiarity with Post-Si validation is a plus.

ACADEMIC CREDENTIALS: 

• Minimum BSEE/CE, or equivalent degree in related engineering disciplines or computer science

LOCATION:  

• Fort Collins, CO

#LI-MR1

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

DESIGN VERIFICATION METHODOLOGY SENIOR ENGINEER

THE ROLE: 

We are looking for an experienced design verification professional to take on the role of DV methodology, infrastructure and automation within the NBIO organization. She/He will be part of a team responsible for developing a scalable DV flow with emphasis on automation, architecture, power and performance. The qualified candidate will work closely with multiple teams and groups on charting verification strategy, automating the verification flow, defining the test bench architecture, and evaluating/deploying new DV methodologies and solutions with the goal of enabling the scalable IP DV strategy and infrastructure needed to support AMD’s aggressive product roadmap. 

THE PERSON: 

• Creative and innovative thinker who loves technical problems.
• Organized, enthusiastic and self-motivated with a strong interest in verification methodologies and automation.
• Be a self-starter, pro-active, and take ownership to drive tasks to completion.
• Excellent communication skills (verbal and written) with strong problem-solving, and attention to detail.
• Ability to work in a multi-discipline team and global setting as a solution enabler.

KEY RESPONSIBILITIES: 

• Work with system/design/DV architects on defining various aspects of the overall IP verification strategy and methodology.
• Identify, develop, and deploy design/DV flow, infrastructure, and automation enhancements.
• Develop and/or enhance in-house tools to improve productivity, metric collection, and tracking.
• Identify performance and productivity bottlenecks and come up with innovative solutions.
• Drive technical initiatives to improve AMD’s capabilities in IP validation/verification, including tool and script development, technical and procedural methodology improvement, and various other internal and cross-functional technical initiatives.
• Architect and develop testbench components as well as test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology.
• Adapt UVM testbenches and DV flows to support emulation and post-silicon activities.
• Evaluate and deploy the latest verification solutions, tools, and methodologies. 

PREFERRED SKILL SET & EXPERIENCE: 

• Senior experience in the ASIC industry including a design verification lead or DV architecture role.
• Deep knowledge of DV infrastructure, Make flow and other automation flows, shell, perl, python, ruby.
• Proficiency in Verilog, SystemVerilog, and C/C++.
• Extensive experience verifying complex designs using UVM, OVM or VMM.
• Expertise in constrained random verification methodologies, metric/coverage driven verification and formal verification.
• Exposure to emulation/HW acceleration for design verification, architectural prototyping, and virtual platforms for SW enablement.
• Familiarity with Jenkins, JIRA, JAMA, GIT, Perforce.
• Familiarity with industry standard high-speed protocols such as PCIe, SATA, USB.
• Experience with verification of Hardware-Firmware interaction is highly desirable.
• Familiarity with Post-Si validation is a plus.

ACADEMIC CREDENTIALS: 

• Minimum BSEE/CE, or equivalent degree in related engineering disciplines or computer science

LOCATION:  

• Fort Collins, CO

#LI-MR1