DFT ATPG Design Engineer

May 10, 2024
Austin, United States
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

AMD’s Cores Organization delivers industry leading CPU’s and caches that are the foundation of AMD’s server, client, and gaming business.  We are looking for an experienced VLSI ATPG design engineer to join this innovative team as a technical expert.  The candidate will be a key contributor and leader for AMD’s next generation cores and caches.  The candidate will join the team based in Fort Collins, CO. 

 

THE PERSON:

The candidate should have strong analytical thinking and problem-solving skills with excellent attention to details.  We work on programs with long timelines, so self-motivation and a commitment to meeting deadlines is required.   We are pushing the envelope on chip performance and manufacture quality, so the status quo must be challenged on every program.  This requires creativity and innovation, but also excellent verbal and written communication skills.  We work in small teams, but we are part of a large cross-site Core’s organization, so teamwork is also vital our success.

 

KEY RESPONSIBILITIES:

  • Provide leadership for a dedicated team of hardware and software engineers to define and implement the CPU-level microarchitecture related to cache hierarchy designs, scan test, and ATPG.
  • Influence and drive improvements in scan architecture, scan coverage, scan test models, and project execution and quality.
  • Write and maintain external specifications for product and test teams to use.
  • Work closely with the Physical Design team members to drive design closure using experience with Netlist analysis, Static Timing, clock domain crossing (CDC) tools on RTL and gate-level netlists, and Static Power analysis tools and flows.
  • Own and deliver scan test patterns, work with product test teams during test bring up phase of the product.
  • Work across global teams to solve complex interactions between IP and SOC build environments.
  • Develop ways to improve our CPU design by increasing quality, by simplifying design complexities through innovation, and by improving our technical interactions with other teams.
  • Solve design and tool problems requiring ground-breaking approaches and champion innovation across the organization.  Create technical presentations for peers and management.
  • Guide and mentor junior engineers.

 PREFERRED EXPERIENCE:

  • Prior leadership experience with ATPG development and pattern delivery, Scan Architecture, and DFT project execution.
  • Strong background using industry standard ATPG tools in novel ways to drive product quality and project execution improvements.
  • Strong understanding of DFT concepts in areas of Scan Test, IEEE 1149.1 and 1500 standards, and MBIST (Memory Built In Self Test).
  • Strong background in ATPG pattern and netlist debug
  • Working knowledge of multi-clock domain and multi-power domain design.
  • Eagerness to learn and grow as a CPU cache array and DFT design engineer.
  • Experience collaborating effectively towards the success of a project by working closely with a diverse team across disciplines

PREFERRED ACADEMIC CREDENTIALS:

  • BS/MS in EE, CS, CSE (or similar), plus 10+ years hardware design experience

 

LOCATION:

Fort Collins, Colorado, USA

 


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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

AMD’s Cores Organization delivers industry leading CPU’s and caches that are the foundation of AMD’s server, client, and gaming business.  We are looking for an experienced VLSI ATPG design engineer to join this innovative team as a technical expert.  The candidate will be a key contributor and leader for AMD’s next generation cores and caches.  The candidate will join the team based in Fort Collins, CO. 

 

THE PERSON:

The candidate should have strong analytical thinking and problem-solving skills with excellent attention to details.  We work on programs with long timelines, so self-motivation and a commitment to meeting deadlines is required.   We are pushing the envelope on chip performance and manufacture quality, so the status quo must be challenged on every program.  This requires creativity and innovation, but also excellent verbal and written communication skills.  We work in small teams, but we are part of a large cross-site Core’s organization, so teamwork is also vital our success.

 

KEY RESPONSIBILITIES:

  • Provide leadership for a dedicated team of hardware and software engineers to define and implement the CPU-level microarchitecture related to cache hierarchy designs, scan test, and ATPG.
  • Influence and drive improvements in scan architecture, scan coverage, scan test models, and project execution and quality.
  • Write and maintain external specifications for product and test teams to use.
  • Work closely with the Physical Design team members to drive design closure using experience with Netlist analysis, Static Timing, clock domain crossing (CDC) tools on RTL and gate-level netlists, and Static Power analysis tools and flows.
  • Own and deliver scan test patterns, work with product test teams during test bring up phase of the product.
  • Work across global teams to solve complex interactions between IP and SOC build environments.
  • Develop ways to improve our CPU design by increasing quality, by simplifying design complexities through innovation, and by improving our technical interactions with other teams.
  • Solve design and tool problems requiring ground-breaking approaches and champion innovation across the organization.  Create technical presentations for peers and management.
  • Guide and mentor junior engineers.

 PREFERRED EXPERIENCE:

  • Prior leadership experience with ATPG development and pattern delivery, Scan Architecture, and DFT project execution.
  • Strong background using industry standard ATPG tools in novel ways to drive product quality and project execution improvements.
  • Strong understanding of DFT concepts in areas of Scan Test, IEEE 1149.1 and 1500 standards, and MBIST (Memory Built In Self Test).
  • Strong background in ATPG pattern and netlist debug
  • Working knowledge of multi-clock domain and multi-power domain design.
  • Eagerness to learn and grow as a CPU cache array and DFT design engineer.
  • Experience collaborating effectively towards the success of a project by working closely with a diverse team across disciplines

PREFERRED ACADEMIC CREDENTIALS:

  • BS/MS in EE, CS, CSE (or similar), plus 10+ years hardware design experience

 

LOCATION:

Fort Collins, Colorado, USA

 


#LI-G11 

 

#LI-HYBRID

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