DFT ATPG Engineer

Apr 24, 2024
Austin, United States
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE: 

As a member of the Cores Austin DFT Team, the successful candidate will own the ATPG responsibilities for the next generation of AMD high performance cores. As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

 

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

  • Interact with PD and Front End Integration team for Scan Insertion
  • Interfacing with the design teams to ensure DFT design rules and guidelines are met
  • ATPG pattern generation 
  • ATPG pattern verification with gate-level simulation 
  • Verification of DFT scan test architecture and features
  • Test coverage and test cost reduction analysis 
  • Post silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE: 

  • Minimum of 8 years direct experience with ATPG.
  • Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
  • Experience in debugging low coverage and DRC fixes
  • Proficient in logic design using Verilog 
  • Experience of debugging test pattern issues
  • Support of Silicon bringup activities
  • Experience with post-silicon debug 
  • Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc
  • Experience with Tessent Scan/ATPG
  • Excellent presentation and inter-communication skills.

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 


#LI-G11 

 

#LI-HYBRID

 




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

As a member of the Cores Austin DFT Team, the successful candidate will own the ATPG responsibilities for the next generation of AMD high performance cores. As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

 

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

  • Interact with PD and Front End Integration team for Scan Insertion
  • Interfacing with the design teams to ensure DFT design rules and guidelines are met
  • ATPG pattern generation 
  • ATPG pattern verification with gate-level simulation 
  • Verification of DFT scan test architecture and features
  • Test coverage and test cost reduction analysis 
  • Post silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE: 

  • Minimum of 8 years direct experience with ATPG.
  • Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
  • Experience in debugging low coverage and DRC fixes
  • Proficient in logic design using Verilog 
  • Experience of debugging test pattern issues
  • Support of Silicon bringup activities
  • Experience with post-silicon debug 
  • Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc
  • Experience with Tessent Scan/ATPG
  • Excellent presentation and inter-communication skills.

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 


#LI-G11 

 

#LI-HYBRID

 

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