Digital Design Engineer

Feb 11, 2024
Markham, Canada
... Not specified
... Intermediate
Full time
... Office work

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

As a member of the PCIe design team, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

 

THE PERSON: 

  • Exhibits relentless commitment to help the team meet quality and development goals on schedule
  • Drives to learn and perform at his or her highest potential in a technical capacity
  • Thrives in both a team environment and in individual contribution
  • Communicates openly and clearly in meetings, presentations, emails, and reports
  • Able to learn independently and acquire new skills required for the job
  • Flexible in working hours to accommodate working with co-workers in different time-zones
  • Creative and innovator and thinker who loves technical problems and detail-oriented tasks

 

KEY RESPONSIBILITIES:

  • Integration and Implementation of the AMDs PCI Express (PCIe) subsystem.
  • IP integration, synthesis, timing, lint and cdc closure to ensure high quality design. 
  • Responsible to implement the design related to test, debug, clocks.
  • Understanding of low power design techniques and have good knowledge of the UPF based power-aware flow.
  • Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.
  • Drive and hands-on flow development, automation, and scripting.
  • Work collaboratively across teams of IP designers, Physical Design team and SoC level leads.
  • Technical and schedule discussion with multi-site engineers and managers 

 

 PREFERRED EXPERIENCE:

  • Understanding of Digital Design in RTL, Verilog HDL
  • Understanding of Synthesis / Linting / CDC tools, equivalence checks
  • Understanding of power saving techniques, including UPF/CPF based power-aware flows and checks.
  • Strong Unix scripting and utilities (Perl/Python/Tcl programming) for analysis and automation.
  • Background and working knowledge in ASIC implementation, familiar with Synopsys and Cadence tools.
  • Background in clocking, reset, power-up sequences and physical design optimization.

 

ACADEMIC CREDENTIALS:

  • Bachelor/master’s in electrical/Computer Engineering/Engineering Science or Computer Science 

LOCATION: Vancouver

 

#LI-TB2

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

As a member of the PCIe design team, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

 

THE PERSON: 

  • Exhibits relentless commitment to help the team meet quality and development goals on schedule
  • Drives to learn and perform at his or her highest potential in a technical capacity
  • Thrives in both a team environment and in individual contribution
  • Communicates openly and clearly in meetings, presentations, emails, and reports
  • Able to learn independently and acquire new skills required for the job
  • Flexible in working hours to accommodate working with co-workers in different time-zones
  • Creative and innovator and thinker who loves technical problems and detail-oriented tasks

 

KEY RESPONSIBILITIES:

  • Integration and Implementation of the AMDs PCI Express (PCIe) subsystem.
  • IP integration, synthesis, timing, lint and cdc closure to ensure high quality design. 
  • Responsible to implement the design related to test, debug, clocks.
  • Understanding of low power design techniques and have good knowledge of the UPF based power-aware flow.
  • Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.
  • Drive and hands-on flow development, automation, and scripting.
  • Work collaboratively across teams of IP designers, Physical Design team and SoC level leads.
  • Technical and schedule discussion with multi-site engineers and managers 

 

 PREFERRED EXPERIENCE:

  • Understanding of Digital Design in RTL, Verilog HDL
  • Understanding of Synthesis / Linting / CDC tools, equivalence checks
  • Understanding of power saving techniques, including UPF/CPF based power-aware flows and checks.
  • Strong Unix scripting and utilities (Perl/Python/Tcl programming) for analysis and automation.
  • Background and working knowledge in ASIC implementation, familiar with Synopsys and Cadence tools.
  • Background in clocking, reset, power-up sequences and physical design optimization.

 

ACADEMIC CREDENTIALS:

  • Bachelor/master’s in electrical/Computer Engineering/Engineering Science or Computer Science 

LOCATION: Vancouver

 

#LI-TB2

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