WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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The Role :  The candidate will be a Lead Member of the PCIeSS design team supporting the definition, specification, system simulation and implementation of future PCIe6, and FUSA for AECG, Servers, Clients, and GPUs. The focus of the activity will be centered around the architecture and documentation of these critical design areas. 

The Person : 

• Will have analytical thinking and inventive skills in combination with a solid understanding of risks and risk mitigation
• Leadership and mentoring/teaching skills
• Strong/effective communication / documentation skills
• Teamwork skills

Responsibilities : 

• Contribute to the definition of protocol architecture optimizing performance, quality, power, timing, latency, area, and other design attributes for PCIe6
• Work with system architects to define/document capabilities for PCIeSS. 
• Drive FUSA capabilities for PCIeSS group. Document requirements and interface/align with designers for a high quality FUSA implementation.
• Develop patents in key areas.
• Participate and contribute to the definition of development flows that improve efficiency and quality of execution 

Preferred Skilled Sets :

• A proven successful track record in architecture and design for PCIe and industry standard open architectures
• Strong documentation insight and skills
• Teaching / mentoring
• Inventive and ability to get innovations into production
• Solid knowledge of industry-standard tools and best-in-class practices for RTL design.

Education Requirements

• Bachelors or Masters in Electrical or Computer Engineering

#LI-DC1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Role :  The candidate will be a Lead Member of the PCIeSS design team supporting the definition, specification, system simulation and implementation of future PCIe6, and FUSA for AECG, Servers, Clients, and GPUs. The focus of the activity will be centered around the architecture and documentation of these critical design areas. 

The Person : 

• Will have analytical thinking and inventive skills in combination with a solid understanding of risks and risk mitigation
• Leadership and mentoring/teaching skills
• Strong/effective communication / documentation skills
• Teamwork skills

Responsibilities : 

• Contribute to the definition of protocol architecture optimizing performance, quality, power, timing, latency, area, and other design attributes for PCIe6
• Work with system architects to define/document capabilities for PCIeSS. 
• Drive FUSA capabilities for PCIeSS group. Document requirements and interface/align with designers for a high quality FUSA implementation.
• Develop patents in key areas.
• Participate and contribute to the definition of development flows that improve efficiency and quality of execution 

Preferred Skilled Sets :

• A proven successful track record in architecture and design for PCIe and industry standard open architectures
• Strong documentation insight and skills
• Teaching / mentoring
• Inventive and ability to get innovations into production
• Solid knowledge of industry-standard tools and best-in-class practices for RTL design.

Education Requirements

• Bachelors or Masters in Electrical or Computer Engineering

#LI-DC1