Director Silicon Design Engineering

Apr 05, 2024
San Jose, United States
... Not specified
... Senior
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




The Person :

  • The ideal candidate will have a strong understanding of digital/analog mixed-signal IP layers with experience in memory interfaces and high-speed transceivers.
  • Lead a team of uArchitect and Logic designers developing memory interfaces, chiplets and chiplet IPs PHY layers and mixed signal IPs.
  • Define innovative and efficient design methodologies from architecture to physical implementation.
  • Work with verification team for test plan/strategy to meet all functional requirements and performance. Work with timing and physical team for timing closure and meet power and area goals
  • Work with analog teams in developing, modelling, and verifying mixed-signal designs.
  • Work with cross functional teams across the company to deliver SOC customer-ready IP products. Work closely with SoC Integration teams to drive high level achievements for IP bounding-box targets.
  • Develop plans and track progress to maintain aggressive development timelines.
  • Own development of comprehensive IP micro-architecture specification documents.
  • Work with partner and peer teams to augment project staff, when required.
  • Multi-task skills will be key to lead IPs across several projects at a time.
  • Pull together regular project status presentations for next level management leadership review. Convert large amounts of data into a clear story to communicate to peers and next level management. Identify risks, develop mitigation strategies & facilitate conflict resolution.
  • Lead internal weekly convergence meetings to resolve technical issues. Drive technical work with partner teams, resolving issues and bug tracking. Drive resolution of technical issues between multi-functional teams: Technology/Library, AMS design, PD, DV & CAD teams.
  • Collaborate with software/hardware and global ops teams to plan silicon validation of IPs.
  • Hire and attract top talent and nurture a strong team collaboration culture and drive creative thinking.

 

Preferred Experience :

  • Proven track record in leading IP design teams and work from concept/feasibility phase to production.  Experience working in a dynamic engineering environment and real-time management skills.
  • track record of cross-functional collaboration as well as hands-on IP development, IP project engineering management.
  • Strong commitment to own/drive IP project development using well-defined metrics.  Work with PM team on execution planning, to track quality metrics, milestone convergence, to assess risk, and ensure plan is on track
  • knowledge of IP front-end development processes, tools/flows and methodologies and life cycle in an IP/SoC workflow:
    • RTL coding and/or IP integration experience.
    • integration knowledge of analog circuits and mixed signal designs.
    • Creating and understanding logic functionalities in terms block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts.
    • Implementing RTL in System Verilog, perform unit level testing, debug tests, SDC and UPF generation.
    • Integrating hard IP and soft IPs including industry standard and proprietary interfaces
    • RTL Lint check, RTL synthesis, Equivalence checking, CDC/VDC/RDC checking and Static Timing Analysis workflows.
  • Full understanding of established and emerging design methodologies and flows from Architecture to digital signoff including ability to build Verilog A/AMS behavioral models for complicated analog/mixed signal blocks.
  • Knowledge of die-to-die link (UCIE, …), Serdes (MIPI C-PHY, D-PHY, SGMII,other..), and DRAM/HBM PHYs (LPDDR4-5-6, system DDR4-5-6, HBM2/HBM3/HBM4/…) design and architectures. Knowledge of DRAM/HBM memory Controllers and protocols is a plus.
  • Experience micro-architecting high-speed IO/SerDes links. Familiarity with clocking architectures and implementations
  • Design experience in advanced CMOS technologies including FinFet process node
  • Experience in lab testing of high-speed memory interfaces and high-speed links is a plus.
  • Excellent written and verbal interpersonal skills. Able to draft and manage technical documentations workflows such as Arch and uArch specs/user guides, with professional quality levels.
  • M.S. or Ph.D in Electrical Engineering and related fields, or equivalent.


 #LI-G11 

 

#LI-HYBRID




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Person :

  • The ideal candidate will have a strong understanding of digital/analog mixed-signal IP layers with experience in memory interfaces and high-speed transceivers.
  • Lead a team of uArchitect and Logic designers developing memory interfaces, chiplets and chiplet IPs PHY layers and mixed signal IPs.
  • Define innovative and efficient design methodologies from architecture to physical implementation.
  • Work with verification team for test plan/strategy to meet all functional requirements and performance. Work with timing and physical team for timing closure and meet power and area goals
  • Work with analog teams in developing, modelling, and verifying mixed-signal designs.
  • Work with cross functional teams across the company to deliver SOC customer-ready IP products. Work closely with SoC Integration teams to drive high level achievements for IP bounding-box targets.
  • Develop plans and track progress to maintain aggressive development timelines.
  • Own development of comprehensive IP micro-architecture specification documents.
  • Work with partner and peer teams to augment project staff, when required.
  • Multi-task skills will be key to lead IPs across several projects at a time.
  • Pull together regular project status presentations for next level management leadership review. Convert large amounts of data into a clear story to communicate to peers and next level management. Identify risks, develop mitigation strategies & facilitate conflict resolution.
  • Lead internal weekly convergence meetings to resolve technical issues. Drive technical work with partner teams, resolving issues and bug tracking. Drive resolution of technical issues between multi-functional teams: Technology/Library, AMS design, PD, DV & CAD teams.
  • Collaborate with software/hardware and global ops teams to plan silicon validation of IPs.
  • Hire and attract top talent and nurture a strong team collaboration culture and drive creative thinking.

 

Preferred Experience :

  • Proven track record in leading IP design teams and work from concept/feasibility phase to production.  Experience working in a dynamic engineering environment and real-time management skills.
  • track record of cross-functional collaboration as well as hands-on IP development, IP project engineering management.
  • Strong commitment to own/drive IP project development using well-defined metrics.  Work with PM team on execution planning, to track quality metrics, milestone convergence, to assess risk, and ensure plan is on track
  • knowledge of IP front-end development processes, tools/flows and methodologies and life cycle in an IP/SoC workflow:
    • RTL coding and/or IP integration experience.
    • integration knowledge of analog circuits and mixed signal designs.
    • Creating and understanding logic functionalities in terms block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts.
    • Implementing RTL in System Verilog, perform unit level testing, debug tests, SDC and UPF generation.
    • Integrating hard IP and soft IPs including industry standard and proprietary interfaces
    • RTL Lint check, RTL synthesis, Equivalence checking, CDC/VDC/RDC checking and Static Timing Analysis workflows.
  • Full understanding of established and emerging design methodologies and flows from Architecture to digital signoff including ability to build Verilog A/AMS behavioral models for complicated analog/mixed signal blocks.
  • Knowledge of die-to-die link (UCIE, …), Serdes (MIPI C-PHY, D-PHY, SGMII,other..), and DRAM/HBM PHYs (LPDDR4-5-6, system DDR4-5-6, HBM2/HBM3/HBM4/…) design and architectures. Knowledge of DRAM/HBM memory Controllers and protocols is a plus.
  • Experience micro-architecting high-speed IO/SerDes links. Familiarity with clocking architectures and implementations
  • Design experience in advanced CMOS technologies including FinFet process node
  • Experience in lab testing of high-speed memory interfaces and high-speed links is a plus.
  • Excellent written and verbal interpersonal skills. Able to draft and manage technical documentations workflows such as Arch and uArch specs/user guides, with professional quality levels.
  • M.S. or Ph.D in Electrical Engineering and related fields, or equivalent.


 #LI-G11 

 

#LI-HYBRID

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