WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

We are searching for a senior technical leader to join the PHY Analog design team, responsible for driving design definition, specification, and implementation of future PHY & Clocking IP, including the next generation clocking.  The successful candidate will also be expected to contribute to advancing Clocking & PHY design methodologies across AMD IO teams.

THE PERSON:

The successful candidate will possess:

• Good technical knowledge and experience of high-speed IO circuits and microarchitecture, including Clocking, GDDR, DDR, and/or SERDES
• Strong and effective communication skills
• Effective at leading and getting results
• Strong cross functional project management skills
• Relevant academic background (M. degree preferred) and at least 18 years’ progressive experience
• Working knowledge of AMD Markets, products and IP portfolio as well general industry awareness

KEY RESPONSIBILITIES:

• Lead the design definition, feasibility, design, and implementation of Clocking IPs
• Lead and grow a team of engineers working on high speed Clocking IPs
• Work with other teams including domain and team leads, architects, SI/PI, Ckt, RTL, SOC, and Si Char/Validation and debug as needed to ensure interlocked execution
• Provide additional over-all design mentorship and contribution to shared methodologies across Custom Analog Clocking teams

PREFERRED EXPERIENCE:

• Experience in high-speed Clocking, GDDR, DDR and/or Serdes design, signaling techniques, RTL design, Modeling of circuit and signal integrity (where applicable)
• Demonstrated ability to define, architect, and implement advanced high-speed IO designs
• Demonstrated ability to recruit and lead teams of engineers
• Experience of advanced analog design and high speed clocking design preferred
• 18 years’ progressive experience preferred

ACADEMIC CREDENTIALS:

• Relevant academic background (Master degree preferred)

#LI-DC1

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

We are searching for a senior technical leader to join the PHY Analog design team, responsible for driving design definition, specification, and implementation of future PHY & Clocking IP, including the next generation clocking.  The successful candidate will also be expected to contribute to advancing Clocking & PHY design methodologies across AMD IO teams.

THE PERSON:

The successful candidate will possess:

• Good technical knowledge and experience of high-speed IO circuits and microarchitecture, including Clocking, GDDR, DDR, and/or SERDES
• Strong and effective communication skills
• Effective at leading and getting results
• Strong cross functional project management skills
• Relevant academic background (M. degree preferred) and at least 18 years’ progressive experience
• Working knowledge of AMD Markets, products and IP portfolio as well general industry awareness

KEY RESPONSIBILITIES:

• Lead the design definition, feasibility, design, and implementation of Clocking IPs
• Lead and grow a team of engineers working on high speed Clocking IPs
• Work with other teams including domain and team leads, architects, SI/PI, Ckt, RTL, SOC, and Si Char/Validation and debug as needed to ensure interlocked execution
• Provide additional over-all design mentorship and contribution to shared methodologies across Custom Analog Clocking teams

PREFERRED EXPERIENCE:

• Experience in high-speed Clocking, GDDR, DDR and/or Serdes design, signaling techniques, RTL design, Modeling of circuit and signal integrity (where applicable)
• Demonstrated ability to define, architect, and implement advanced high-speed IO designs
• Demonstrated ability to recruit and lead teams of engineers
• Experience of advanced analog design and high speed clocking design preferred
• 18 years’ progressive experience preferred

ACADEMIC CREDENTIALS:

• Relevant academic background (Master degree preferred)

#LI-DC1