WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Performing synthesis and netlisting tasks such as; SDC development, scan insertion, functional and timing ECO implementation, formal verification RTL vs gate, etc.
- Timing/SDC constraints generation and management. Performing constraint analysis and debug, using industry standard tools.
- Performing RTL synthesis and clock tree synthesis.
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
- Chip level design and integration activities.
- Conduct low power design and implementation on power aware synthesis and PNR.
- Collaborate with Physical Design team on Floor Plan, ram placement, timing closure and resolve congestion, etc.
PREFERRED EXPERIENCE:
- Experience in ASIC design.
- Proficient with EDA tools like DC, ICC2 and FC.
- Proficient in static timing analysis (STA) tools and techniques for timing closure.
- Understanding of floorplan and layout techniques for foundry rule compliant.
- Voltage domain check knowledge is a plus.
- Scripting language experience: TCL, Perl, or Python.
- Exposure to DFT is an asset.
- Good communication and teamwork skills.
- Strong analytical and problem-solving skills.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering.
#LI-IA1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Performing synthesis and netlisting tasks such as; SDC development, scan insertion, functional and timing ECO implementation, formal verification RTL vs gate, etc.
- Timing/SDC constraints generation and management. Performing constraint analysis and debug, using industry standard tools.
- Performing RTL synthesis and clock tree synthesis.
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
- Chip level design and integration activities.
- Conduct low power design and implementation on power aware synthesis and PNR.
- Collaborate with Physical Design team on Floor Plan, ram placement, timing closure and resolve congestion, etc.
PREFERRED EXPERIENCE:
- Experience in ASIC design.
- Proficient with EDA tools like DC, ICC2 and FC.
- Proficient in static timing analysis (STA) tools and techniques for timing closure.
- Understanding of floorplan and layout techniques for foundry rule compliant.
- Voltage domain check knowledge is a plus.
- Scripting language experience: TCL, Perl, or Python.
- Exposure to DFT is an asset.
- Good communication and teamwork skills.
- Strong analytical and problem-solving skills.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering.
#LI-IA1
#LI-Hybrid