WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 

We are looking for a Fellow-level Engineer to join our team to develop world-class products around discrete, console and mobile GPUs.  In this role you will be engaged with Graphics architects, micro architecture, RTL, CAD/Methodology, and internal stakeholders to define end to end Power Optimization Methodology, PVT Corners, timing methodology that require technically analyzing, defining usage cases, and mapping across a broad spectrum of technologies to ensure a well-defined methodology to achieve PPA uplift across a spectrum of GPU products. In this role you will provide a cohesive technical vision of the required PPA improvement methodology. 

THE PERSON: 

You will possess very strong problem-solving skills and bring broad experience in methodology, with a strong, self-motivated work ethic. 

KEY RESPONSIBILITIES: 

• Define and drive PPA uplift methodologies for GPU products 

• Develop and deploy end to end power optimization methodology for Physical Design Implementation 
• Define PVT corners, device frequency scaling, frequency targets for next generation GPUs in leading foundry technology nodes 
• Deep knowledge of micro architecture, power optimization methodologies, Synthesis, Place and Route, Top level Clocking structure and Timing closure. 
• Proven track record of tapeout experience with leading technology nodes like 10nm, 7nm and 5nm 
• Excellent communication skills and strong collaboration across multiple business units 

PREFERRED EXPERIENCE: 

• Deep experience in physical design and methodology preferred 
• Experience working seamlessly across engineering disciplines and geographies to deliver excellent results 

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering  

LOCATION: 

San Jose, CA

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

We are looking for a Fellow-level Engineer to join our team to develop world-class products around discrete, console and mobile GPUs.  In this role you will be engaged with Graphics architects, micro architecture, RTL, CAD/Methodology, and internal stakeholders to define end to end Power Optimization Methodology, PVT Corners, timing methodology that require technically analyzing, defining usage cases, and mapping across a broad spectrum of technologies to ensure a well-defined methodology to achieve PPA uplift across a spectrum of GPU products. In this role you will provide a cohesive technical vision of the required PPA improvement methodology. 

THE PERSON: 

You will possess very strong problem-solving skills and bring broad experience in methodology, with a strong, self-motivated work ethic. 

KEY RESPONSIBILITIES: 

• Define and drive PPA uplift methodologies for GPU products 

• Develop and deploy end to end power optimization methodology for Physical Design Implementation 
• Define PVT corners, device frequency scaling, frequency targets for next generation GPUs in leading foundry technology nodes 
• Deep knowledge of micro architecture, power optimization methodologies, Synthesis, Place and Route, Top level Clocking structure and Timing closure. 
• Proven track record of tapeout experience with leading technology nodes like 10nm, 7nm and 5nm 
• Excellent communication skills and strong collaboration across multiple business units 

PREFERRED EXPERIENCE: 

• Deep experience in physical design and methodology preferred 
• Experience working seamlessly across engineering disciplines and geographies to deliver excellent results 

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering  

LOCATION: 

San Jose, CA

#LI-IL1

#LI-HYBRID