Firmware Design Engineer

Nov 29, 2023
Vancouver, Canada
... Not specified
... Intermediate
Full time
... Office work
Overview

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_


Responsibilities

FIRMWARE DESIGN ENGINEER

THE ROLE:
The Memory IO team is looking for a passionate and experienced Firmware designers for the development of high-speed LPDDR, DDR and inter-chip IO IPs.  Be a part of the definition, design, and development and productization phase of industry-leading Memory PHYs and interface IP.  This opportunity includes enabling of new PHY designs at the microarchitecture, firmware/hardware co-design, and algorithm design level. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge Memory interfaces.  

 

THE PERSON:
Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills.

 
KEY RESPONSIBILITIES:


• Firmware design and development of DDR PHY & DRAM Training steps
• Firmware development of DDR PHY for ATE Testing, IP Char & SoC Power
• Pre-silicon FW coding and simulation against Architectural and RTL models
• Post-silicon lab bring-up and optimization of DDR Init and Run Time FW
• Post-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin
• Working with SoC/Product firmware teams to define features and specs

 
PREFERRED EXPERIENCE:


• Excellent knowledge of C, C++ and any scripting language ; knowledge of Verilog and Python is a plus
• Ability to adapt learn new toolsets and frameworks is required
• Strong understanding of synchronization techniques (handshakes, message passing) ; knowledge of hardware level clocking and synchronization is a plus
• Post-silicon experience developing firmware on real hardware is required. Experience with SERDES, DDR, Memory Controller, or MAC Design experience is preferred
• Strong understanding of computer organization/architecture.
• Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.
• Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)

 
ACADEMIC CREDENTIALS:

  • Bachelor’s degree in electrical or computer engineering is strongly desired. Master's or PhD degree is a plus.

#LI-DP1


Qualifications

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

FIRMWARE DESIGN ENGINEER

THE ROLE:
The Memory IO team is looking for a passionate and experienced Firmware designers for the development of high-speed LPDDR, DDR and inter-chip IO IPs.  Be a part of the definition, design, and development and productization phase of industry-leading Memory PHYs and interface IP.  This opportunity includes enabling of new PHY designs at the microarchitecture, firmware/hardware co-design, and algorithm design level. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge Memory interfaces.  

 

THE PERSON:
Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills.

 
KEY RESPONSIBILITIES:


• Firmware design and development of DDR PHY & DRAM Training steps
• Firmware development of DDR PHY for ATE Testing, IP Char & SoC Power
• Pre-silicon FW coding and simulation against Architectural and RTL models
• Post-silicon lab bring-up and optimization of DDR Init and Run Time FW
• Post-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin
• Working with SoC/Product firmware teams to define features and specs

 
PREFERRED EXPERIENCE:


• Excellent knowledge of C, C++ and any scripting language ; knowledge of Verilog and Python is a plus
• Ability to adapt learn new toolsets and frameworks is required
• Strong understanding of synchronization techniques (handshakes, message passing) ; knowledge of hardware level clocking and synchronization is a plus
• Post-silicon experience developing firmware on real hardware is required. Experience with SERDES, DDR, Memory Controller, or MAC Design experience is preferred
• Strong understanding of computer organization/architecture.
• Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.
• Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)

 
ACADEMIC CREDENTIALS:

  • Bachelor’s degree in electrical or computer engineering is strongly desired. Master's or PhD degree is a plus.

#LI-DP1

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