Formal Design Verification Engineer - Memory Controller - 163562

May 19, 2022
Santa Clara, United States
... Not specified
... Senior
Full time
... Office work

What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

The Unified Memory Controller(UMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available.


What You'll Be Doing

As an FV Engineer, you will be leading the complete Formal Verification for single or multiple design blocks and IPs.

  • Identifying blocks suitable for Formal
  • Working with block designers to understand micro-architectural details
  • Identifying and implementing Formal properties
  • Applying abstraction techniques
  • Signing off with bound analysis and coverage
  • Participating in test-plan and test-bench reviews
  • Apply multiple formal methodologies to improve overall UMC verification quality.
  • Mentoring/leading junior engineer

What We Need To See

  • Bachelor's or Master's Degree in Electrical and/or Computer Engineering with at least 3 years of work experience in digital integrated circuit (IC) design verification or other equivalent experience. 
  • Strong knowledge in Verilog, System Verilog, and System Verilog Assertion Language (SVA)
  • Understanding of Formal verification concepts (FPV, FCA, RTL –to- RTL equivalence, Connectivity..)
  • Requires strong Computer Architecture knowledge
  • Hands-on experience with industry-standard Formal verification tools (JasperGold, VC Formal or Questa Formal)
  • Strong coding skills in Python/Perl or other industry-standard scripting languages
  • Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out
  • Strong communication skills and the ability to work independently as well as in a cross-site team environment


Ways To Stand Out From The Crowd

  • Prior experience with DRAM controllers and DDR phys.  
  • Experience with the application of Formal verification techniques including abstractions
  • Familiarity with bug-hunting strategies and coverage analysis
  • Profound understanding of Formal verification engines






      Requisition Number: 163562 
      Country: United States State: California City: Santa Clara 
      Job Function: Design

      Benefits offered are described here.

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