High Speed IO Design Engineer

Jun 29, 2022
Santa Clara, United States
... Not specified
... Intermediate
Full time
... Office work


What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

The Role: 

The candidate will be a member of the Memory I/O design team designing High Speed IO circuits and supporting the definition, specification, system simulation and implementation of future DDR, LPDDR, GDDR IPs. The focus of the activity will be centered around the circuit design of critical high-speed analog and digital blocks, definition of specifications for the high speed data path.

 

The Person: 

  • Will have analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation
  • Strong/effective communication skills
  • Enthusiastic team-first mentality

 

Responsibilities:

  • Design circuits for High Speed IOs that include Transmitter, Receiver – CTLE/DFE, DLL, DAC, OpAmp, Comparator and voltage regulators.
  • Contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for DDR, LPDDR, GDDR PHYs
  • Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
  • Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
  • Participate and contribute to the definition of development flows that improve efficiency and quality of execution 

 

Preferred Skilled Sets:

  • A proven successful track record in circuit design for High Speed IOs
  • Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
  • Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
  • Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
  • Ability to dig into RTL or FW code supporting the custom circuit implementation

 

Education Requirements

  • Bachelors, Masters or PHD in Electrical or Computer Engineering

 

 

#LI-IL1


Requisition Number: 169206 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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