IP Design Engineer

Mar 03, 2024
Markham, Canada
... Not specified
... Intermediate
Full time
... Office work

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.  

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

  • Collaborate with architects and hardware engineers to understand the new design features to be implemented
  • Implement various digital design components such as VDCI, FIFOs, (GP)IOs, SDP/AXI repeaters, reference clock network, etc.
  • Integrating AMD internal IPs RTL/DV components into SoC environment
  • Review static design analysis reports such as CDC, Lint, VSI/VC-LP, and timing reports, drive closure of sign-off checks
    Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
  • Drive design and methodology improvements across teams to improve overall program execution
  • Participate in defining and implementing the design power-intent (power-gating / voltage islands)
  • Debug test failures to determine the root cause; work with RTL and DV engineers to resolve design defects and correct test issues

 

PREFERRED EXPERIENCE: 

  • Proficiency with Verilog RTL design languages
  • Proficient in debugging RTL code using simulation tools
  • ASIC DV experience in reusable verification methodology such as UVM
  • Knowledge of chip bus interfaces such as SDP, AXI and various standard peripherals & interfaces is a plus
  • Have hands-on experience in chip level Design/Integration activities
  • Have in-depth knowledge of entire design process from design specification, defining architecture, micro-architecture, RTL design and functional verification, Synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug
  • Some exposure to DFT is a strong plus
  • Strong background in the C++ language, preferably on Linux platform 
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language 
  • Scripting language experience: Perl, TCL, Ruby, Makefile, shell preferred
  • Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in Electrical Engineering 

 

#LI-TB1

#LI-Hybrid

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.  

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

  • Collaborate with architects and hardware engineers to understand the new design features to be implemented
  • Implement various digital design components such as VDCI, FIFOs, (GP)IOs, SDP/AXI repeaters, reference clock network, etc.
  • Integrating AMD internal IPs RTL/DV components into SoC environment
  • Review static design analysis reports such as CDC, Lint, VSI/VC-LP, and timing reports, drive closure of sign-off checks
    Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
  • Drive design and methodology improvements across teams to improve overall program execution
  • Participate in defining and implementing the design power-intent (power-gating / voltage islands)
  • Debug test failures to determine the root cause; work with RTL and DV engineers to resolve design defects and correct test issues

 

PREFERRED EXPERIENCE: 

  • Proficiency with Verilog RTL design languages
  • Proficient in debugging RTL code using simulation tools
  • ASIC DV experience in reusable verification methodology such as UVM
  • Knowledge of chip bus interfaces such as SDP, AXI and various standard peripherals & interfaces is a plus
  • Have hands-on experience in chip level Design/Integration activities
  • Have in-depth knowledge of entire design process from design specification, defining architecture, micro-architecture, RTL design and functional verification, Synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug
  • Some exposure to DFT is a strong plus
  • Strong background in the C++ language, preferably on Linux platform 
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language 
  • Scripting language experience: Perl, TCL, Ruby, Makefile, shell preferred
  • Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in Electrical Engineering 

 

#LI-TB1

#LI-Hybrid

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