WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

THE ROLE: 

As a Lab Liaison Design Engineer in the Unified Memory Controller (UMC) (DRAM Controller) team you will participate in representing and enabling the high-performance integrated memory controllers used in diverse markets such as client APUs and server CPUs with support for DDR5/LPDDR5 DRAM technologies across different variants. 

• You will be working on state-of-the-art DRAM controller technologies.
• You will be working in the lab to enable the DRAM controller and related features out through to the interface. This involves scripting, Logic Analyzers and Oscilloscopes.
• You will be working on new SOC technologies such as EPYC and RYZEN.
• This position enables you to have a low-level working knowledge of features and RTL of the UMC (DRAM controller) through production.
• You will be working with pseudo code - FSDL (Firmware Sequence Descriptor Language) – which is used to mimic Firmware sequences for controller functions such as initialization and power management. This will provide overall exposure of the DRAM controller.
• You will be working with documentation that accurately describes the FSDL and RTL work that is involved in development.

When you join our UMC team in a Lab Liaison Design Engineer, you will take ownership and contribute in many ways including these areas:

• Maintain and further establish AMD's technological leadership position through UMC design enablement and development.
• Respond to problems using cutting edge approaches.
• Collaborate closely with other team members while working closely with verification and implementation team members to debug the design.

THE PERSON:

Ideally you would bring the following experience and attributes to our team:

• Recent experience with DRAM controller development and DDR DRAM technologies such as DDR4/DDR5/LPDDR4/LPDDR5 is highly desired.
• Very good understanding of digital design concepts, computer architecture and logic design
• Strong skills in logic debug in a lab setting.
• Knowledge of, or experience in, functional design verification or design is desired.
• Proficient in reading Verilog
• Ability to program with scripting languages such as Python or Perl is a plus;
• Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;
• Proven interpersonal skills, leadership and teamwork;
• Excellent writing skills in the English language, editing and organizational skills required;
• Strong attention to detail;
• Represents AMD to the outside technical community, partners and vendors
• Skilled at prioritization and multi-tasking;
• Good understanding of engineering terminology used within the semiconductor industry.

KEY RESPONSIBLITIES:

• Familiar with the UMC DRAM Controller architecture and design.
• Interact with the design verification team and propose testing methods for verifying the design.
• Become familiar with FSDL for use in in sequences such as: Initialization and power management.

PREFERRED EXPERIENCE:

• Verilog RTL
• DDR DRAM device and DIMM technologies.
• DFI (DRAM PHY Interface) specification.

ACADEMIC CREDENTIALS:

• Bachelor’s degree desired with emphasis in Electrical Engineering
• Master’s degree with emphasis in Electrical Engineering a plus

Location:

• Austin, Tx
• Boston, Ma area can be considered

#LI-MR1

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

As a Lab Liaison Design Engineer in the Unified Memory Controller (UMC) (DRAM Controller) team you will participate in representing and enabling the high-performance integrated memory controllers used in diverse markets such as client APUs and server CPUs with support for DDR5/LPDDR5 DRAM technologies across different variants. 

• You will be working on state-of-the-art DRAM controller technologies.
• You will be working in the lab to enable the DRAM controller and related features out through to the interface. This involves scripting, Logic Analyzers and Oscilloscopes.
• You will be working on new SOC technologies such as EPYC and RYZEN.
• This position enables you to have a low-level working knowledge of features and RTL of the UMC (DRAM controller) through production.
• You will be working with pseudo code - FSDL (Firmware Sequence Descriptor Language) – which is used to mimic Firmware sequences for controller functions such as initialization and power management. This will provide overall exposure of the DRAM controller.
• You will be working with documentation that accurately describes the FSDL and RTL work that is involved in development.

When you join our UMC team in a Lab Liaison Design Engineer, you will take ownership and contribute in many ways including these areas:

• Maintain and further establish AMD's technological leadership position through UMC design enablement and development.
• Respond to problems using cutting edge approaches.
• Collaborate closely with other team members while working closely with verification and implementation team members to debug the design.

THE PERSON:

Ideally you would bring the following experience and attributes to our team:

• Recent experience with DRAM controller development and DDR DRAM technologies such as DDR4/DDR5/LPDDR4/LPDDR5 is highly desired.
• Very good understanding of digital design concepts, computer architecture and logic design
• Strong skills in logic debug in a lab setting.
• Knowledge of, or experience in, functional design verification or design is desired.
• Proficient in reading Verilog
• Ability to program with scripting languages such as Python or Perl is a plus;
• Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;
• Proven interpersonal skills, leadership and teamwork;
• Excellent writing skills in the English language, editing and organizational skills required;
• Strong attention to detail;
• Represents AMD to the outside technical community, partners and vendors
• Skilled at prioritization and multi-tasking;
• Good understanding of engineering terminology used within the semiconductor industry.

KEY RESPONSIBLITIES:

• Familiar with the UMC DRAM Controller architecture and design.
• Interact with the design verification team and propose testing methods for verifying the design.
• Become familiar with FSDL for use in in sequences such as: Initialization and power management.

PREFERRED EXPERIENCE:

• Verilog RTL
• DDR DRAM device and DIMM technologies.
• DFI (DRAM PHY Interface) specification.

ACADEMIC CREDENTIALS:

• Bachelor’s degree desired with emphasis in Electrical Engineering
• Master’s degree with emphasis in Electrical Engineering a plus

Location:

• Austin, Tx
• Boston, Ma area can be considered

#LI-MR1