Lead DDR PHY Post Si Engineer- 160201

May 18, 2022
Austin, United States
... Not specified
... Senior
Full time
... Office work


What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Lead DDR PHY Post Si Engineer

 

The Person:

Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills

 

The Role:

The DDR IP team is looking for a passionate and experienced Post-Silicon Validation Engineer for driving the bring-up, debug and development of high-speed LPDDR and DDR PHY IPs.  You will be a part of the design & FW team actively participating in the development phase of industry-leading PHYs and set yourself up for success in the end-to-end support of the post-silicon teams involved in feature bring-up, DDR Training algorithms tuning, mixed-signal IP Char, ATE screens debug and system stability & reliability testing. This opportunity includes working alongside the microarchitecture, firmware/hardware design, algorithm development & circuit teams and closing the loop with the post-silicon lessons learnt and feedback.

 

RESPONSIBILITIES:

  • Be an integral part of the DDR PHY design and FW teams influencing and developing DDR Training algorithms
  • In Post-Silicon, collaborate with Platform, ATE, Mixed Signal IP Char and Firmware teams for DDR system bring-up and features validation
  • Be a key point of contact from design team in triaging, debugging and driving critical DDR Post-Si issues to closure across the eco system
  • Track the DDR Init and Training algorithms tuning in Post Si and feeding back to design and FW team for alignment
  • Work in the lab with all equipment to debug and perform root cause analysis
  • Document and sign-off the DDR IP for customer release and drive the lessons learnt to closure
  • Enable DDR debug tools, like functional eye plotting, with script-based test automation in Python or other scripting tools

 

Preference & Skill Sets :

  • Deep experience in DDR/LPDDR memory interface PHY Silicon Validation and System debug is required.
  • Strong understanding of JEDEC standards for DDR technologies such as DDR5 and LPDDR5
  • Expertise in coding DDR Training algorithms and bring-up sequences and Post-Si tuning is needed
  • Experience working with SIPI simulation teams and understanding of the DDR Interface challenges and system timing budget
  • Experience with JTAG debuggers and hands on lab experience with instruments like High-Speed Oscilloscopes, BERTs, VNAs, Spectrum Analyzers, etc.
  • Excellent knowledge of Python Scripting to automate tests and mine data from log files and C/C++ language
  • Passion to get to the root of complex problems by collaborating with various teams including design and FW

 

EDUCATION:

  • Bachelor's degree in Electrical or Computer engineering is required. Master's or PhD degree is a plus.

 

Location : Austin TX

 

#LI-IL1
 


Requisition Number: 160201 
Country: United States State: Texas City: Austin 
Job Function: Design
  

Benefits offered are described here.

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