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THE ROLE:

The CPG HW Platform team is looking for Lead SIPI Engineer. Ideal candidate would be working with key architects to make system level tradeoffs to come up with the robust SIPI designs for the next generation HW Platforms. Lead SIPI engineer will need to work with Packaging SIPI team, Memory IO SIPI team and Serdes teams.

THE PERSON:

This person should be self-driven and demonstrated technical leadership skills with successful HW Systems designs from the architecture phase to manufacturing. To be able to develop methodologies and processes. A strong written and verbal communicator with strong problem solving skills along with professional interpersonal communication skills.

KEY RESPONSIBILITIES:

• System-level signal integrity simulation and optimization on PCB stackup, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise.
• Power integrity analysis for state of art system designs, which include but not limited to layout model extraction, transient noise analysis (ADS, HSPICE) to meet specifications, decoupling strategy and analysis. SSN(Simultaneous Switching Noise) analysis for I/O (DDR5, LPDDR5, etc.)
• Generate Layout routing rules for Serdes interface up to 112G data rate, High speed memory interfaces (LPDDR4, LPDDR5) and all other high speed interfaces
• Opportunity to work on high speed and RF signal trace routing, via optimization,
• Crosstalk analysis and reduction on-die, on-silicon interposer, on-package and on-PCB.
• Full-wave modeling of vias, connectors, package and PCB channels, and various system components using 3D full-wave EM tools.
• Document and sign off PCB designs prior to the fab release
• Lab measurements to characterize the SIPI performance and close loop correlation with simulation modeling and results including Serdes interface tuning and characterizations

PREFERRED EXPERIENCE:

• Solid background on transmission-line theory and computational electromagnetics.
• Industry working experiences on signal integrity and power integrity in one or more of signaling standards, PCIe gen4/5, Ethernet, DDR5, LPDDR5, HBM2/2e/3.
• Experiences with SI tools, HSPICE, HFSS/Q3D, PowerSI/PowerDC, ADS or similar.
• Hands-on lab experiences using high speed real time scope, VNA, TDR, and spectrum analyzer.
• Familiar with RF designs, high speed package designs, or high speed PCB designs will be a plus.

ACADEMIC CREDENTIALS:

• Master or Ph.D Degree in Electrical Engineering or Computer Science

LOCATION:

San Jose, CA

#LI-DW1

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

The CPG HW Platform team is looking for Lead SIPI Engineer. Ideal candidate would be working with key architects to make system level tradeoffs to come up with the robust SIPI designs for the next generation HW Platforms. Lead SIPI engineer will need to work with Packaging SIPI team, Memory IO SIPI team and Serdes teams.

THE PERSON:

This person should be self-driven and demonstrated technical leadership skills with successful HW Systems designs from the architecture phase to manufacturing. To be able to develop methodologies and processes. A strong written and verbal communicator with strong problem solving skills along with professional interpersonal communication skills.

KEY RESPONSIBILITIES:

• System-level signal integrity simulation and optimization on PCB stackup, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise.
• Power integrity analysis for state of art system designs, which include but not limited to layout model extraction, transient noise analysis (ADS, HSPICE) to meet specifications, decoupling strategy and analysis. SSN(Simultaneous Switching Noise) analysis for I/O (DDR5, LPDDR5, etc.)
• Generate Layout routing rules for Serdes interface up to 112G data rate, High speed memory interfaces (LPDDR4, LPDDR5) and all other high speed interfaces
• Opportunity to work on high speed and RF signal trace routing, via optimization,
• Crosstalk analysis and reduction on-die, on-silicon interposer, on-package and on-PCB.
• Full-wave modeling of vias, connectors, package and PCB channels, and various system components using 3D full-wave EM tools.
• Document and sign off PCB designs prior to the fab release
• Lab measurements to characterize the SIPI performance and close loop correlation with simulation modeling and results including Serdes interface tuning and characterizations

PREFERRED EXPERIENCE:

• Solid background on transmission-line theory and computational electromagnetics.
• Industry working experiences on signal integrity and power integrity in one or more of signaling standards, PCIe gen4/5, Ethernet, DDR5, LPDDR5, HBM2/2e/3.
• Experiences with SI tools, HSPICE, HFSS/Q3D, PowerSI/PowerDC, ADS or similar.
• Hands-on lab experiences using high speed real time scope, VNA, TDR, and spectrum analyzer.
• Familiar with RF designs, high speed package designs, or high speed PCB designs will be a plus.

ACADEMIC CREDENTIALS:

• Master or Ph.D Degree in Electrical Engineering or Computer Science

LOCATION:

San Jose, CA

#LI-DW1