Low Power Design Optimization Engineer

Apr 19, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SENIOR SILICON DESIGN ENGINEER 

 

THE ROLE:

We keep improving PPA of every graphics chip and especially focus on their power optimization. As the team member, you will take the responsibility to provide accurate power reporting flow, power optimization solution of block design, exploration on power saving feature of EDA tools and so on. You will have access to cutting-edge technology/tools/process. Join us if you have much interest in power optimization or want to develop your competence in a wide range of block design/DV/Synthesize/P&R/….

 

 

THE PERSON:

Low power design optimization engineer should have much interest in low power optimization. He will be involved in many aspects of IC design. Work closely with RTL Design team, design verification team and backend physical design teams across multiple sites. Good communication skill and team spirit. Strong trouble shooting capability and self-motivation.

 

 

KEY RESPONSIBILITIES:

  • perform power test definition, development, profiling, correlation to games/apps/use-cases.
  • perform power flow running, track power trend along with design changes.
  • perform analysis to find power bugs, drive and lead design team to fix.
  • explore advance synthesis and place&route methodology to further reduce power.
  • check RTL design implementation and micro architecture to find opportunities to reduce power.
  • explore any new opportunities from platform, software, system, package, architecture, micro architecture, RTL, implementation.
  • keep tracking industry and academic leading-edge technologies and adopt some applicable methodologies into our designs.
  • adopt advanced power management methodologies. adopt advanced power delivery techniques.

 

PREFERRED EXPERIENCE:

  • BS or MS degree in Computer Science, Software Engineering, Electrical Engineering, Integrated Circuit Engineering or an equivalent
  • 2-3 years of experience in design in digital ASIC chips. knowledge on CPU, GPU, network, Video/audio, router, communication or advanced and complex chips.
  • knowledge on CPU, GPU, network, Video/audio, router, communication or advanced and complex chips.
  • hands-on experience and skills on design implementation from RTL, synthesis, PnR stages.
  • PPA analysis and optimization experience, knowledge and skills.
  • big data analysis and complex problem solve capability 
  • cross team communication and collaboration
  • Proficiency in flow development and scripting (PERL, PYTHON, SHELL) is strong plus
  • hard-working and self-motivated

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

#LI-NS1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SENIOR SILICON DESIGN ENGINEER 

 

THE ROLE:

We keep improving PPA of every graphics chip and especially focus on their power optimization. As the team member, you will take the responsibility to provide accurate power reporting flow, power optimization solution of block design, exploration on power saving feature of EDA tools and so on. You will have access to cutting-edge technology/tools/process. Join us if you have much interest in power optimization or want to develop your competence in a wide range of block design/DV/Synthesize/P&R/….

 

 

THE PERSON:

Low power design optimization engineer should have much interest in low power optimization. He will be involved in many aspects of IC design. Work closely with RTL Design team, design verification team and backend physical design teams across multiple sites. Good communication skill and team spirit. Strong trouble shooting capability and self-motivation.

 

 

KEY RESPONSIBILITIES:

  • perform power test definition, development, profiling, correlation to games/apps/use-cases.
  • perform power flow running, track power trend along with design changes.
  • perform analysis to find power bugs, drive and lead design team to fix.
  • explore advance synthesis and place&route methodology to further reduce power.
  • check RTL design implementation and micro architecture to find opportunities to reduce power.
  • explore any new opportunities from platform, software, system, package, architecture, micro architecture, RTL, implementation.
  • keep tracking industry and academic leading-edge technologies and adopt some applicable methodologies into our designs.
  • adopt advanced power management methodologies. adopt advanced power delivery techniques.

 

PREFERRED EXPERIENCE:

  • BS or MS degree in Computer Science, Software Engineering, Electrical Engineering, Integrated Circuit Engineering or an equivalent
  • 2-3 years of experience in design in digital ASIC chips. knowledge on CPU, GPU, network, Video/audio, router, communication or advanced and complex chips.
  • knowledge on CPU, GPU, network, Video/audio, router, communication or advanced and complex chips.
  • hands-on experience and skills on design implementation from RTL, synthesis, PnR stages.
  • PPA analysis and optimization experience, knowledge and skills.
  • big data analysis and complex problem solve capability 
  • cross team communication and collaboration
  • Proficiency in flow development and scripting (PERL, PYTHON, SHELL) is strong plus
  • hard-working and self-motivated

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

#LI-NS1

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