Memory Lead / Post Si - Validation Architect - 164206
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
MEMORY LEAD / POST SILICON VALIDATION ARCHITECT
The Memory debug Engineer is a role with significant cross-Org impact and visibility and will be recognized as an authority and a trustworthy advisor in memory/memory hierarchy and software by senior technical leaders across multiple organizations, top group management level and respected by peers.
The position requires a solid combination of technical expertise and strategic acumen, ability to work effectively across functional and organizational boundaries and the ability to communicate effectively across customer, technical, business & executive audiences.
The successful candidate work across multiple organizations as an action and results oriented thought leader with a passion for driving technology direction & strategy.
- Drive the cross-org SW-HW pathfinding & tech readiness actions across teams to initiate, direct and mature the technology innovations at the juncture of memory/memory hierarchy and software, determine the value and dependencies through POR and on a solid path to execution
- Develop the strategy and detailed plans for high potential technologies
- Develop & own technology roadmap for software-visible-memory-technologies across HW (IPs, SoCs) & SW
- Proactively identify ambiguities/opens and drive one-voice (go/no-go) on technology direction, and recommendations by working closely with senior technologists and stakeholders across multiple orgs, and external customers/partners.
- Drive standardization strategy & efforts as applicable
- Kickoff/work through HW & SW teams to kickoff new innovations or PoCs
- Drive/Manage impactful technology forum(s) with HW-SW experts
- Work with, and establish trust across a diverse array of stakeholders across software, Business Units and HW teams, and external customers and ecosystem partners
- Proven track record of taking ownership and driving technology directions & innovations into products
- Proven track record of working with & influencing across broad set of stakeholders
- Highly Technically savvy across broad spectrum of software and architecture with prior hands-on experience, technology details, and be comfortable driving discussions with other technologists & BUs
- Deep familiarity with at least one or more of the following: memory or memory hierarchy, tiering architectures, Compute-in/near-memory, Non-volatile memory
- Deep familiarity with at least one or more of the following: computer architecture, datacenter/cloud architecture & platforms, GPU architecture, PC or network platforms/architecture
- Prior experience with driving a technology/technical-strategy & plan agenda to fruition
- Prior experience driving a technology agenda and/or cross-group strategic initiatives successfully
- Experience presenting to senior level audiences
- Hands-on familiarity with one or more of the following: operating system internals, memory management, AI, micro-architecture
- Prior experience participating in and shaping an industry standard, or driving convergence with multiple external partners
- Prior experience creating & driving technology roadmaps
- Masters in CS/EE with 12+ years’ experience or Bachelors with 14+ years’ experience
Requisition Number: 164206
Country: United States State: California City: Roseville
Job Function: Design
Benefits offered are described here.
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