Memory System RTL Performance Engineer

Mar 10, 2024
Santa Clara, Cuba
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE: 

The System IP team is responsible for the development of AMD’s client and server memory controllers, and Infinity Fabric interconnect. The Infinity Fabric is part of every new AMD product being developed across Data Center (Server and Instinct), Client, Graphics, and Semi-Custom markets.


The role involves RTL performance analysis and microbenchmarking for the Infinity Fabric IP performance team. The engineer will work closely with the architecture, design and modeling teams working on high-performance SOC interconnect designs. He or she will drive RTL microbenchmarking plans at the IP level, and support performance debug at the SOC level. In addition, the engineer will work closely with C++ performance modeling efforts to maintain correlation with the RTL.

 

THE PERSON: 

The ideal candidate for this role is technically sound in computer architecture with a high degree of interest in memory system architectures. Successful candidates have a passion for learning and growing their technical boundaries. Excellent communication and data summarization skills are highly preferred, as is a willingness to work in a dynamic cross-site, cross-team environment.

 

KEY RESPONSIBILITIES: 

  • Register transfer level (RTL) performance analysis and microbenchmarking for the Infinity Fabric memory system composed of the Interconnect and Memory Controller.
  • Work closely with the architecture, design, and modeling teams working on high-performance systems-on-chip (SOC) memory system designs.
  • Develop and maintain performance microbenchmarks for the Infinity Fabric IP, and debug performance bottlenecks in RTL simulations at IP or SOC level.
  • Conduct theoretical analysis of memory system optimizations, set up benchmarks to run in RTL simulations, maintain or enhance regression scripts to automate them
  • Debug cases where benchmarks fail their performance metrics, identifying design bottle necks and proposing solutions.
  • Work on debug tools and visualization solutions
  • Fix issues seen in the performance benchmarking environment to deliver the highest performing Interconnect and Memory Controller IP under given design parameters for planned production.
  • Mentor junior engineers
  • Develop and maintain IP performance debug tools.
  • Collaborate with C++ performance model team for correlation effort.

 

PREFERRED EXPERIENCE: 

  • Proven experience in RTL microbenchmarking and Performance Validation domains
  • Deep experience with memory system and memory controller design and architecture
  • Excellent knowledge of Verilog and System Verilog
  • Working knowledge of C, C++ and a scripting language like Perl or Python
  • Good understanding of multi-processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches.
  • Excellent debugging and analytical skills
  • Exposure to leadership or mentorship is an asset 

 

ACADEMIC CREDENTIALS: 

  • Masters degree in Computer engineering/Electrical Engineering, with a focus on Computer Architecture. Advanced degree preferred.

 #LI-G11 

 

#LI-HYBRID




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

The System IP team is responsible for the development of AMD’s client and server memory controllers, and Infinity Fabric interconnect. The Infinity Fabric is part of every new AMD product being developed across Data Center (Server and Instinct), Client, Graphics, and Semi-Custom markets.


The role involves RTL performance analysis and microbenchmarking for the Infinity Fabric IP performance team. The engineer will work closely with the architecture, design and modeling teams working on high-performance SOC interconnect designs. He or she will drive RTL microbenchmarking plans at the IP level, and support performance debug at the SOC level. In addition, the engineer will work closely with C++ performance modeling efforts to maintain correlation with the RTL.

 

THE PERSON: 

The ideal candidate for this role is technically sound in computer architecture with a high degree of interest in memory system architectures. Successful candidates have a passion for learning and growing their technical boundaries. Excellent communication and data summarization skills are highly preferred, as is a willingness to work in a dynamic cross-site, cross-team environment.

 

KEY RESPONSIBILITIES: 

  • Register transfer level (RTL) performance analysis and microbenchmarking for the Infinity Fabric memory system composed of the Interconnect and Memory Controller.
  • Work closely with the architecture, design, and modeling teams working on high-performance systems-on-chip (SOC) memory system designs.
  • Develop and maintain performance microbenchmarks for the Infinity Fabric IP, and debug performance bottlenecks in RTL simulations at IP or SOC level.
  • Conduct theoretical analysis of memory system optimizations, set up benchmarks to run in RTL simulations, maintain or enhance regression scripts to automate them
  • Debug cases where benchmarks fail their performance metrics, identifying design bottle necks and proposing solutions.
  • Work on debug tools and visualization solutions
  • Fix issues seen in the performance benchmarking environment to deliver the highest performing Interconnect and Memory Controller IP under given design parameters for planned production.
  • Mentor junior engineers
  • Develop and maintain IP performance debug tools.
  • Collaborate with C++ performance model team for correlation effort.

 

PREFERRED EXPERIENCE: 

  • Proven experience in RTL microbenchmarking and Performance Validation domains
  • Deep experience with memory system and memory controller design and architecture
  • Excellent knowledge of Verilog and System Verilog
  • Working knowledge of C, C++ and a scripting language like Perl or Python
  • Good understanding of multi-processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches.
  • Excellent debugging and analytical skills
  • Exposure to leadership or mentorship is an asset 

 

ACADEMIC CREDENTIALS: 

  • Masters degree in Computer engineering/Electrical Engineering, with a focus on Computer Architecture. Advanced degree preferred.

 #LI-G11 

 

#LI-HYBRID

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