MTS DFT Engineer
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
Design-for-Testability (DFT) Engineer
As a Design-for-Testability (DFT) Engineer, you will be part of a leading team while implementing and verifying the DFT architecture and features. We are seeking an Engineer with a strong understanding of Design-for-Test (DFT) methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, STA , etc.).
We are on the lookout for a dynamic DFT Engineer to join our growing team. Do you enjoy Design-for-Test methodologies and DFT verification? If yes, please read on for additional details regarding this position! Our team is looking for someone who can self-start and who is able to work efficiently within a team environment and independently to drive tasks to completion, all while demonstrating excellent oral, written and interpersonal communication skills!
This DFT Engineer will be responsible for Scan/Jtag/boundary scan insertion and ATPG pattern generation as well as, Memory BIST logic generation, implementation and verification. Additional responsibilities include:
- DFT IP RTL and MBIST implementation
- Scan insertion and ATPG patterns verification with gate level simulation
- Test coverage and test cost reduction analysis
- Post silicon support to ensure successful bringup and enhance yield learning
- Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
- Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design
Master degree preferred, and/or working experience in the ASIC DFT area
Boxborough, MA , Austin, TX or Markham, ON
Requisition Number: 171681
Country: United States State: Massachusetts City: Boxborough
Job Function: Design
Benefits offered are described here.
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