MTS Physical verification Engineer

May 09, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


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MTS PHYSICAL VERIFICATION ENGINEER 

 

Job Description

As a member of our physical verification team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing, design-for-yield, design-for-reliability and lithography) at the chip and block level. You will collaborate with the CAD, Foundry Operations teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on pad ring, bump, RDL design, and working with the package and floorplan teams.

 

Technical Requirements

 

  • 8+ years of physical design experience with emphasis on physical verification
  • Real chip tapeout experience in sub-14nm technology nodes with a track record of successful signoff
  • Strong knowledge of physical verification flows and methodology
  • Knowledge of all aspects of ASIC physical design
  • Scripting skills to debug flow related issues and make enhancements as appropriate
  • Expertise in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
  • Experience in planning physical verification for closure.
  • Experience in leading and mentoring a team in physical verification.
  • Ability to work cross-functionally with various teams and be productive under aggressive schedules.

 

ACADEMIC CREDENTIALS:

  • Qualification: Bachelors or Masters in Electronics/Electrical Engineering 

LOCATION:

Hyderabad/Bangalore

 

#LI-RG2




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS PHYSICAL VERIFICATION ENGINEER 

 

Job Description

As a member of our physical verification team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing, design-for-yield, design-for-reliability and lithography) at the chip and block level. You will collaborate with the CAD, Foundry Operations teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on pad ring, bump, RDL design, and working with the package and floorplan teams.

 

Technical Requirements

 

  • 8+ years of physical design experience with emphasis on physical verification
  • Real chip tapeout experience in sub-14nm technology nodes with a track record of successful signoff
  • Strong knowledge of physical verification flows and methodology
  • Knowledge of all aspects of ASIC physical design
  • Scripting skills to debug flow related issues and make enhancements as appropriate
  • Expertise in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
  • Experience in planning physical verification for closure.
  • Experience in leading and mentoring a team in physical verification.
  • Ability to work cross-functionally with various teams and be productive under aggressive schedules.

 

ACADEMIC CREDENTIALS:

  • Qualification: Bachelors or Masters in Electronics/Electrical Engineering 

LOCATION:

Hyderabad/Bangalore

 

#LI-RG2

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