WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

MTS SILICON DESIGN ENGINEER  - FullChip FloorPlan (FCFP) 

THE ROLE: 

AMD is looking for an experienced SOC FullChip FloorPlan (FCFP) Engineer to deliver on the next generation of cutting-edge graphics designs. 

 As part of the RTG SOC team, our team will be responsible for prioritization and managing the implementation activities on Graphics SOC's. This is built up from basics like how work spaces are setup, how blocks are coordinated and interacted in a System-On-Chip environment, Performance Power Area signoff, 3DIC flows, how the tools/flows are developed to automate processes. As always, the team is dedicated to come up with innovative solution to overcome new challenges related to specific project requirements and time-to-market.

THE PERSON:  

You have a passion for modern, complex processor design implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES:  

• Responsible for Full Chip Floorplan or Full chip block level in technologies of 5nm and below.
• To be part of the Physical Design team for projects with GHz freq range and cutting edge technologies.
• Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
• Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
• Experienced in deep sub-micron designs ( below 5Nm).
• Experienced in physical design tasks with deep technical knowledge in all (floor planning, placement, clock-tree-syntheses CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
• Experienced in Full Chip PNR & Partitioning / Bump Placement.
• Experience in Low power and high performance design.
• Able and willing to work with teams across sites and with cross-functional teams.
• Strong debug skills and Automation savvy.
• Expert in tools Cadence Encounter/Synopsys ICC / Cadence Innovus.
• Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Ability to understand design constraints and implement high-quality layouts.
• Multiple Tape out support experience will be an added advantage.
• The ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced working environment.

PREFERRED EXPERIENCE:  

• 9+ years of relevant experience in the fields of Floorplaning, Physical design,  or related fields.
• Strong analytical, debug, and problem-solving skills in resolving Floorplan challenge
• Capable of working in a cross functional and multi-site team environment spanning multiple time zones.    
• Demonstrate good analysis and problem-solving skills. Out-of-the-box thinking
• Capability to create scripts to improve floorplan efficiency and workflow.
• Experience with custom 3DIC Designs is a plus.

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  - FullChip FloorPlan (FCFP) 

THE ROLE: 

AMD is looking for an experienced SOC FullChip FloorPlan (FCFP) Engineer to deliver on the next generation of cutting-edge graphics designs. 

 As part of the RTG SOC team, our team will be responsible for prioritization and managing the implementation activities on Graphics SOC's. This is built up from basics like how work spaces are setup, how blocks are coordinated and interacted in a System-On-Chip environment, Performance Power Area signoff, 3DIC flows, how the tools/flows are developed to automate processes. As always, the team is dedicated to come up with innovative solution to overcome new challenges related to specific project requirements and time-to-market.

THE PERSON:  

You have a passion for modern, complex processor design implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES:  

• Responsible for Full Chip Floorplan or Full chip block level in technologies of 5nm and below.
• To be part of the Physical Design team for projects with GHz freq range and cutting edge technologies.
• Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
• Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
• Experienced in deep sub-micron designs ( below 5Nm).
• Experienced in physical design tasks with deep technical knowledge in all (floor planning, placement, clock-tree-syntheses CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
• Experienced in Full Chip PNR & Partitioning / Bump Placement.
• Experience in Low power and high performance design.
• Able and willing to work with teams across sites and with cross-functional teams.
• Strong debug skills and Automation savvy.
• Expert in tools Cadence Encounter/Synopsys ICC / Cadence Innovus.
• Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Ability to understand design constraints and implement high-quality layouts.
• Multiple Tape out support experience will be an added advantage.
• The ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced working environment.

PREFERRED EXPERIENCE:  

• 9+ years of relevant experience in the fields of Floorplaning, Physical design,  or related fields.
• Strong analytical, debug, and problem-solving skills in resolving Floorplan challenge
• Capable of working in a cross functional and multi-site team environment spanning multiple time zones.    
• Demonstrate good analysis and problem-solving skills. Out-of-the-box thinking
• Capability to create scripts to improve floorplan efficiency and workflow.
• Experience with custom 3DIC Designs is a plus.

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering