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MTS SILICON DESIGN ENGINEER  

Job description, Role responsibilities:

As a member of our physical design team, you will be working on hierarchical floorplan implementation of SOC. You will collaborate with the SOC architects, IP architects, block owners, SOC Front End team as part of floorplan optimization. You will be responsible to work directly with the block owners during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on floorplan, padring, bump, RDL design, and working with the package and block owners.

Required skills & experience

1. 8+ years of physical design experience with emphasis on physical verification
2. Knowledge of Hierarchical SOC floorplan implementation.
3. Strong knowledge of physical design flows and methodology
4. Knowledge of all aspects of ASIC physical design
5. Scripting skills to debug flow related issues and make enhancements as appropriate
6. Expertise in industry standard tools used for physical design such as ICC etc.
7. Experience in leading and mentoring a team in fullchip floorplan implementation
8. Experience in STA is a plus.

#LI-PK2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  

Job description, Role responsibilities:

As a member of our physical design team, you will be working on hierarchical floorplan implementation of SOC. You will collaborate with the SOC architects, IP architects, block owners, SOC Front End team as part of floorplan optimization. You will be responsible to work directly with the block owners during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on floorplan, padring, bump, RDL design, and working with the package and block owners.

Required skills & experience

1. 8+ years of physical design experience with emphasis on physical verification
2. Knowledge of Hierarchical SOC floorplan implementation.
3. Strong knowledge of physical design flows and methodology
4. Knowledge of all aspects of ASIC physical design
5. Scripting skills to debug flow related issues and make enhancements as appropriate
6. Expertise in industry standard tools used for physical design such as ICC etc.
7. Experience in leading and mentoring a team in fullchip floorplan implementation
8. Experience in STA is a plus.

#LI-PK2