WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

MTS SILICON DESIGN ENGINEER  

THE ROLE: 

The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for additional tasks that are related to SOC design closure.

KEY RESPONSIBILITIES:  

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified 
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases 
• Estimate the time required to write the new feature tests and any required changes to the test environment 
• Build the directed and random verification tests 
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  

• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements 

PREFERRED EXPERIENCE:  

•             Bachelor/Master Degree in Electronics Engineering and at least 10+ years’ experience in complex ASIC Design projects.

•             Have in depth knowledge of entire physical design process from floorplan till GDS generation

•             Good Exposure to Physical Verification Process

•             Have hands-on experience in latest deep-sub-micron technologies 14nm and  below

•             Hands –on experience in PnR tools Synopsys ICC/Cadence Encounter etc.

•             Experience in low power designs and handling congestion or timing critical tiles will be preferred

•             Should be a quick learner and have good attention to detail

•             Experience in ECO implementation preferred

•             Scripting skills in Perl/Python etc.

•             Must have good communication & problem-solving skills.

•             Should be able to handle PnR tasks with minimal supervision

•             Should be able to lead a small team technically and drive the assigned tasks to closure

DESIRED SKILL

1. SoC implementation expertise. Multimillion gates integration.

2. Physical Synthesis, Constraints validation.

3. Floorplanning, Power planning.

4.  Scan Synthesis, Scan re-order.

5. Static Timing analysis (STA).

6. Analysis: IR, EM, Noise.

7. Physical Verification.

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

LI-PM2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  

THE ROLE: 

The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for additional tasks that are related to SOC design closure.

KEY RESPONSIBILITIES:  

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified 
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases 
• Estimate the time required to write the new feature tests and any required changes to the test environment 
• Build the directed and random verification tests 
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  

• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements 

PREFERRED EXPERIENCE:  

•             Bachelor/Master Degree in Electronics Engineering and at least 10+ years’ experience in complex ASIC Design projects.

•             Have in depth knowledge of entire physical design process from floorplan till GDS generation

•             Good Exposure to Physical Verification Process

•             Have hands-on experience in latest deep-sub-micron technologies 14nm and  below

•             Hands –on experience in PnR tools Synopsys ICC/Cadence Encounter etc.

•             Experience in low power designs and handling congestion or timing critical tiles will be preferred

•             Should be a quick learner and have good attention to detail

•             Experience in ECO implementation preferred

•             Scripting skills in Perl/Python etc.

•             Must have good communication & problem-solving skills.

•             Should be able to handle PnR tasks with minimal supervision

•             Should be able to lead a small team technically and drive the assigned tasks to closure

DESIRED SKILL

1. SoC implementation expertise. Multimillion gates integration.

2. Physical Synthesis, Constraints validation.

3. Floorplanning, Power planning.

4.  Scan Synthesis, Scan re-order.

5. Static Timing analysis (STA).

6. Analysis: IR, EM, Noise.

7. Physical Verification.

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

LI-PM2