MTS Silicon Design Engineer

Feb 10, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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MTS DFT Design Engineer

 

THE ROLE:

  • As a member of the S3 SoC DFT Team, the successful candidate will own the DFT micro-architecture and RTL implementation using Verilog/System Verilog for the next gen of AMD S3 SoCs.) 
  • Position includes test creation/development, characterization, data analysis, and silicon debug of DFT Scan/ATPG test in leading edge process technologies. AMD's environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology! 

THE PERSON:

  • A successful person in this role would be able to work in a collaborative team environment working with the RTL designers and other Verification Engineers to find creative ways to accelerate the identification of functional defects
  • Strong self-driving ability, Should have excellent communication skills (both written and oral)
  • Strong problem-solving skills

 

KEY RESPONSIBILITIES:

  • Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT RTL at the SoC level
  • Working closely with the ATPG team for coverage support, with the DV team on helping debugging and root-causing the test failures and with the PD team on DFT timing closure
  •  

PREFERRED EXPERIENCE:

  • Experience in DFT architecture for complex chips
  • Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration
  • Proficient in doing basic unit-level verification using simulations.
  • Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
  • Must have experience with integration of various IPs into complex SOCs.
  • Exposure to Static timing analysis & Timing closure is required.
  • Any prior experience with microprocessor designs is a plus.
  • Scan/ATPG patterns & test flows development, debug, test and characterization
  • Pre-Silicon test planning & validation, Engagement with Design
  • Post Silicon Bring up of test patterns leading to optimization for mass production enablement
  • Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies
  • Optimization of test flows for increased quality and cost improvement
  • Analysis of part failures leading to test coverage and yield improvement
  • Analysis of characterization data across PVT
  • Excellent hands-on debug skills and scripting skills are critical.
  • Must have good communication skills and the ability to work in a worldwide team environment.
  • Knowledge & experience of low power concepts, clock gating, power gating is a plus
  • Experience with post-silicon bring up is a plus

 

ACADEMIC CREDENTIALS:

  • E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
  • 8+  years’ experience in DFT design

#LI-NF1

 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS DFT Design Engineer

 

THE ROLE:

  • As a member of the S3 SoC DFT Team, the successful candidate will own the DFT micro-architecture and RTL implementation using Verilog/System Verilog for the next gen of AMD S3 SoCs.) 
  • Position includes test creation/development, characterization, data analysis, and silicon debug of DFT Scan/ATPG test in leading edge process technologies. AMD's environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology! 

THE PERSON:

  • A successful person in this role would be able to work in a collaborative team environment working with the RTL designers and other Verification Engineers to find creative ways to accelerate the identification of functional defects
  • Strong self-driving ability, Should have excellent communication skills (both written and oral)
  • Strong problem-solving skills

 

KEY RESPONSIBILITIES:

  • Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT RTL at the SoC level
  • Working closely with the ATPG team for coverage support, with the DV team on helping debugging and root-causing the test failures and with the PD team on DFT timing closure
  •  

PREFERRED EXPERIENCE:

  • Experience in DFT architecture for complex chips
  • Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration
  • Proficient in doing basic unit-level verification using simulations.
  • Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
  • Must have experience with integration of various IPs into complex SOCs.
  • Exposure to Static timing analysis & Timing closure is required.
  • Any prior experience with microprocessor designs is a plus.
  • Scan/ATPG patterns & test flows development, debug, test and characterization
  • Pre-Silicon test planning & validation, Engagement with Design
  • Post Silicon Bring up of test patterns leading to optimization for mass production enablement
  • Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies
  • Optimization of test flows for increased quality and cost improvement
  • Analysis of part failures leading to test coverage and yield improvement
  • Analysis of characterization data across PVT
  • Excellent hands-on debug skills and scripting skills are critical.
  • Must have good communication skills and the ability to work in a worldwide team environment.
  • Knowledge & experience of low power concepts, clock gating, power gating is a plus
  • Experience with post-silicon bring up is a plus

 

ACADEMIC CREDENTIALS:

  • E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
  • 8+  years’ experience in DFT design

#LI-NF1

 

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