MTS Silicon Design Engineer

Feb 15, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




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THE ROLE:

  • As Part of the SOC design team you will have technical responsibility for IP/sub-system development, integration efforts. You will work closely with IP development teams and SOC design and verification teams.
  • Throughout the project you will be involved in SOC and IP design and feature enhancements, top-level SOC latency and performance impact.
  • You will lead a discipline within design team and will be responsible for overseeing or performing structural checks such as verilog lint checks, and power domain and clock domain checks as appropriate.
  • You will work with verification teams for simulation and debug of issues related to the subsystem design.
  • You will work with front-end integration teams on synthesis of the SOC top-level netlist and collaborate with physical design.

THE PERSON:

  • Strong self-driving ability
  • Should have excellent communication skills (both written and oral)
  • Strong problem-solving skills

 

KEY RESPONSIBILITIES:

  • IP/subsystem level design and integration
  • Integration of IP, SOC level fabric, voltage and clock crossings, clocks, resets, fuses, I/O
  • Execute on RTL design and coding for various sections for the SOC and related logic.
  • Static verification of design (RTL, CDC, Power, Connectivity)

 

PREFERRED EXPERIENCE:

  • Experience in Verilog RTL development with industry tools in a CPU, SOC, or ASIC environment 
  • Experience in ARM based SOC design and Architecture.
  • SOC Integration
  • SOC architecture understanding.
  • System bus protocol understanding (e.g. AXI, PCIe etc)
  • Experience in power implementation methodology, UPF
  • Static timing analysis
  • Experience working with physical design team and aware of physical design requirements.
  • Comfort with Scripting such as Ruby, Perl, Shell and TCL is a plus
  • Expertise in formal verification techniques and tools

 

ACADEMIC CREDENTIALS:

  • 10+ years of experience in SOC/Subsystem Design and Verilog RTL Development
  • BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

 

LOCATION:

Job location Bangalore

 

#LI-NF1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

------------------------

THE ROLE:

  • As Part of the SOC design team you will have technical responsibility for IP/sub-system development, integration efforts. You will work closely with IP development teams and SOC design and verification teams.
  • Throughout the project you will be involved in SOC and IP design and feature enhancements, top-level SOC latency and performance impact.
  • You will lead a discipline within design team and will be responsible for overseeing or performing structural checks such as verilog lint checks, and power domain and clock domain checks as appropriate.
  • You will work with verification teams for simulation and debug of issues related to the subsystem design.
  • You will work with front-end integration teams on synthesis of the SOC top-level netlist and collaborate with physical design.

THE PERSON:

  • Strong self-driving ability
  • Should have excellent communication skills (both written and oral)
  • Strong problem-solving skills

 

KEY RESPONSIBILITIES:

  • IP/subsystem level design and integration
  • Integration of IP, SOC level fabric, voltage and clock crossings, clocks, resets, fuses, I/O
  • Execute on RTL design and coding for various sections for the SOC and related logic.
  • Static verification of design (RTL, CDC, Power, Connectivity)

 

PREFERRED EXPERIENCE:

  • Experience in Verilog RTL development with industry tools in a CPU, SOC, or ASIC environment 
  • Experience in ARM based SOC design and Architecture.
  • SOC Integration
  • SOC architecture understanding.
  • System bus protocol understanding (e.g. AXI, PCIe etc)
  • Experience in power implementation methodology, UPF
  • Static timing analysis
  • Experience working with physical design team and aware of physical design requirements.
  • Comfort with Scripting such as Ruby, Perl, Shell and TCL is a plus
  • Expertise in formal verification techniques and tools

 

ACADEMIC CREDENTIALS:

  • 10+ years of experience in SOC/Subsystem Design and Verilog RTL Development
  • BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

 

LOCATION:

Job location Bangalore

 

#LI-NF1

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