WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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Job Title: Physical Verification Methodology Engineer

Location: Bangalore/Hyderabad

About Us:

AMD is at the forefront of the chip-making industry, dedicated to advancing technology through innovation and excellence in engineering. We are seeking a highly skilled Physical Verification Methodology Engineer to develop and enhance verification methodologies and support our design teams through successful tape-outs.

THE ROLE: 

As a Physical Verification Methodology Engineer, you will be responsible for developing, implementing, and maintaining robust physical verification methodologies. You will collaborate with design teams to ensure smooth verification processes and provide support throughout the tape-out phase. Your role will be pivotal in enhancing the efficiency and reliability of our verification flows. 

THE PERSON: 

You are a team player who has excellent interpersonal skills and experience collaborating with other engineers located in different sites and timezones. You have strong analytical and problem-solving skills, willingness to learn and ready to take on problems. You are highly motivated to push the envelope and technically supervise the junior engineers within the team.

KEY RESPONSIBILITIES: 

• Develop and refine physical verification methodologies, including DRC, LVS, and ERC, to meet design requirements and industry standards.
• Provide comprehensive support to design teams, ensuring seamless integration of verification methodologies into the design flow.
• Assist in resolving complex verification issues and guide teams through debugging processes.
• Work closely with EDA tool vendors to enhance tool capabilities and address specific verification challenges.
• Automate verification processes through scripting and tool customization to improve efficiency and accuracy.
• Generate detailed documentation and training materials for design teams.
• Ensure compliance with industry standards and best practices in physical verification.
• Participate in tape-out reviews and provide critical feedback to ensure successful tape-outs.

Qualifications:

• Master’s/Bachelor’s Degree in Electronics Engineering
• 7-11 years of experience in CAD flow and methodology development on advanced nodes such as 7nm and 5nm
• Extensive experience in physical verification and methodology development within the semiconductor industry.
• Proficiency with industry-standard verification tools such as Calibre, Mentor Graphics, or ICV , Synopsys.
• Strong debugging skills and in-depth knowledge of DRC/LVS/ERC methodologies.
• Experience with scripting languages (TCL, Perl, Python) for automation purposes.
• Excellent problem-solving abilities and attention to detail.
• Strong communication and collaboration skills.

Preferred Experience :

• Knowledge of PowerVia and 3DStack concepts.
• Proven track record in supporting design teams through successful tape-outs.
• Familiarity with layout editing tools such as DesignREV and ICVWB

#LI-SR4

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Title: Physical Verification Methodology Engineer

Location: Bangalore/Hyderabad

About Us:

AMD is at the forefront of the chip-making industry, dedicated to advancing technology through innovation and excellence in engineering. We are seeking a highly skilled Physical Verification Methodology Engineer to develop and enhance verification methodologies and support our design teams through successful tape-outs.

THE ROLE: 

As a Physical Verification Methodology Engineer, you will be responsible for developing, implementing, and maintaining robust physical verification methodologies. You will collaborate with design teams to ensure smooth verification processes and provide support throughout the tape-out phase. Your role will be pivotal in enhancing the efficiency and reliability of our verification flows. 

THE PERSON: 

You are a team player who has excellent interpersonal skills and experience collaborating with other engineers located in different sites and timezones. You have strong analytical and problem-solving skills, willingness to learn and ready to take on problems. You are highly motivated to push the envelope and technically supervise the junior engineers within the team.

KEY RESPONSIBILITIES: 

• Develop and refine physical verification methodologies, including DRC, LVS, and ERC, to meet design requirements and industry standards.
• Provide comprehensive support to design teams, ensuring seamless integration of verification methodologies into the design flow.
• Assist in resolving complex verification issues and guide teams through debugging processes.
• Work closely with EDA tool vendors to enhance tool capabilities and address specific verification challenges.
• Automate verification processes through scripting and tool customization to improve efficiency and accuracy.
• Generate detailed documentation and training materials for design teams.
• Ensure compliance with industry standards and best practices in physical verification.
• Participate in tape-out reviews and provide critical feedback to ensure successful tape-outs.

Qualifications:

• Master’s/Bachelor’s Degree in Electronics Engineering
• 7-11 years of experience in CAD flow and methodology development on advanced nodes such as 7nm and 5nm
• Extensive experience in physical verification and methodology development within the semiconductor industry.
• Proficiency with industry-standard verification tools such as Calibre, Mentor Graphics, or ICV , Synopsys.
• Strong debugging skills and in-depth knowledge of DRC/LVS/ERC methodologies.
• Experience with scripting languages (TCL, Perl, Python) for automation purposes.
• Excellent problem-solving abilities and attention to detail.
• Strong communication and collaboration skills.

Preferred Experience :

• Knowledge of PowerVia and 3DStack concepts.
• Proven track record in supporting design teams through successful tape-outs.
• Familiarity with layout editing tools such as DesignREV and ICVWB

#LI-SR4