MTS Silicon Design Engineer

Sep 10, 2022
Edinburgh, United Kingdom
... Not specified
... Intermediate
Full time
... Office work


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

We are adding to our Data Centre design team in Edinburgh. This is a fantastic opportunity for an engineer with a passion for front end RTL design algorithmic acceleration on ASIC and FPGA to join a team with access to world-class tools and infrastructure to work on the next generation of accelerated SmartNICs and other ground-breaking products for the data centre.

About You

For this senior role within the development team, the ideal candidate will have a track record of technical success in RTL design on products for high performance computation and networking, making the decisions needed to maximise performance while minimising power and chip area. They should be comfortable working in a cross-team environment across multiple geographies, enjoy working in a team and sharing skills and experience with teammates both locally, and globally from potentially different cultural backgrounds. They will be an excellent communicator, both verbally and in writing.

 

Qualifications;


•    Degree or better in Electronic Engineering, Computer science, or related subject

Skills and Experience
•    Significant experience in VHDL/Verilog/SystemVerilog ASIC and/or FPGA RTL design required.

•    Experience in modernn ASIC front end design flows and tools (including synthesis, lint, CDC, RDC and constraints) would be an advantage.
•    Experience in the architecture, implementation or verification of networking IP, subsystems and systems would be an advantage.

•    Experience in implementation or use of PCIe would be an advantage.
•    Experience in high-level synthesis in C, C++ or OpenCL (beneficial).
•    Experience in other areas of heterogenous computing, including smart networking and smart storage, would be an advantage.
•    Familiarity with Xilinx tools (including Vivado, Vivado HLS, and Vitis) would be an advantage

 

 

#LI-DS3


Requisition Number: 182021 
Country: United Kingdom Province: Scotland City: Edinburgh 
Job Function: Design  
 

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