MTS Silicon Design Engineer

Feb 01, 2024
Hsinchu, Taiwan
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




The Role:

We are seeking a highly skilled Semiconductor Engineer with a minimum of 5-7 years of experience, expertise in parasitic resistance, capacitance extraction (PEX), Electromigration (EM) and IR Drop (IR) analysis, and proficiency in Unix shell environments, Perl, and Python scripting. The successful candidate will play a pivotal role in analyzing and optimizing semiconductor devices, ensuring robust performance under real-world conditions. Responsibilities include advanced PEX methodologies, capacitance modeling, EM analysis, IR Drop effects understanding, coupled with the ability to leverage Unix shell environments and scripting languages such as Perl and Python. This team is essential to the success of AMD as a growing company. It is a very exciting environment, and you will be working with the very best in our technology.  You will be working on some of the most exciting projects the industry has to offer.

 

The Person:

  • In-depth knowledge of semiconductor device physics and fabrication processes, strong analytical and problem-solving skills related to semiconductor device performance, ability to collaborate effectively with design, layout, and verification teams, exceptional written and oral communication skills in English.

Key Responsibilities:

  • Interface with design teams (including Design, Enablement, CAD, Yield, Project Management) across AMD to capture Process Design Kit (PDK) requirements.
  • Develop and install key technology files which include DRC, LVS, Spice, PEX and EMIR
  • Design new regression tests to increase QA coverage of PDK.
  • Benchmark PDKs across various manufacturing partners (i.e. how does device performance compare?)
  • Create and monitor PDK testing and prevent design flow interruptions.
  • Communicate PDK requirements to foundry partners and negotiate release schedules.
  • Communicate and document all PDK releases to AMD design & enablement teams.
  • Ensure quick turn-around times to address all urgent PDK disruptions.
  • Triage PDK issues and drive to resolution.

Preferred Skillset and Experience:

  • Proficiency in industry-standard EDA tools for PEX, capacitance modeling, and EMIR analysis, specifically StarRC, QRC, Totem, Aapche, …etc..
  • Hands-on experience in designing and implementing strategies to mitigate Electromigration effects in semiconductor designs and familiarity with reliability analysis methodologies related to EMIR effects.
  • Knowledge of advanced techniques for IR Drop minimization and optimization.
  • Experience with IR Drop analysis techniques and tools.
  • Experience with SPICE simulation and familiarity with industry-standard modeling techniques.
  • Proficiency in Unix shell environments, Perl, and Python scripting.

Academic Credentials:

  • MSEE/MSCS with minimum 5 years’ experience or BSEE/BSCS with minimum 7 years’ experience
  • Proven experience in PEX and EMIR analysis for semiconductor designs.

#LI-SC1 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Role:

We are seeking a highly skilled Semiconductor Engineer with a minimum of 5-7 years of experience, expertise in parasitic resistance, capacitance extraction (PEX), Electromigration (EM) and IR Drop (IR) analysis, and proficiency in Unix shell environments, Perl, and Python scripting. The successful candidate will play a pivotal role in analyzing and optimizing semiconductor devices, ensuring robust performance under real-world conditions. Responsibilities include advanced PEX methodologies, capacitance modeling, EM analysis, IR Drop effects understanding, coupled with the ability to leverage Unix shell environments and scripting languages such as Perl and Python. This team is essential to the success of AMD as a growing company. It is a very exciting environment, and you will be working with the very best in our technology.  You will be working on some of the most exciting projects the industry has to offer.

 

The Person:

  • In-depth knowledge of semiconductor device physics and fabrication processes, strong analytical and problem-solving skills related to semiconductor device performance, ability to collaborate effectively with design, layout, and verification teams, exceptional written and oral communication skills in English.

Key Responsibilities:

  • Interface with design teams (including Design, Enablement, CAD, Yield, Project Management) across AMD to capture Process Design Kit (PDK) requirements.
  • Develop and install key technology files which include DRC, LVS, Spice, PEX and EMIR
  • Design new regression tests to increase QA coverage of PDK.
  • Benchmark PDKs across various manufacturing partners (i.e. how does device performance compare?)
  • Create and monitor PDK testing and prevent design flow interruptions.
  • Communicate PDK requirements to foundry partners and negotiate release schedules.
  • Communicate and document all PDK releases to AMD design & enablement teams.
  • Ensure quick turn-around times to address all urgent PDK disruptions.
  • Triage PDK issues and drive to resolution.

Preferred Skillset and Experience:

  • Proficiency in industry-standard EDA tools for PEX, capacitance modeling, and EMIR analysis, specifically StarRC, QRC, Totem, Aapche, …etc..
  • Hands-on experience in designing and implementing strategies to mitigate Electromigration effects in semiconductor designs and familiarity with reliability analysis methodologies related to EMIR effects.
  • Knowledge of advanced techniques for IR Drop minimization and optimization.
  • Experience with IR Drop analysis techniques and tools.
  • Experience with SPICE simulation and familiarity with industry-standard modeling techniques.
  • Proficiency in Unix shell environments, Perl, and Python scripting.

Academic Credentials:

  • MSEE/MSCS with minimum 5 years’ experience or BSEE/BSCS with minimum 7 years’ experience
  • Proven experience in PEX and EMIR analysis for semiconductor designs.

#LI-SC1 

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