MTS Silicon Design Engineer

Apr 13, 2024
Hyderabad, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




MTS SILICON DESIGN ENGINEER

  

THE ROLE: 

As a member of the PPA optimization team, you will work on new physical design flow methodology, automation and regression to release quality instructions to PD block team and will work closely with the PD tile, integration and CAD teams across various geographies to achieve first pass silicon success.

  

THE PERSON:  

  • A successful person in this role would be able to work in a collaborative team environment working with other physical design teams to find creative ways to accelerate and improve PPA
  • Strong self-driving ability, should have excellent communication skills (both written and oral)

  

KEY RESPONSIBILITIES:  

  • Automation to refine and improve design PPA (Power, Performance, Area), to ensure a high quality design environment
  • Ability to organize and present complex technical information in a crisp and concise manner.
  • Interact with other PPA (equivalent) teams internal to AMD
  • Identify best practices across AMD and industry to update and improve flow/project settings
  • To increase the competitiveness of each stage in AMD design flow
  • Ability to work with multi-level functional teams across various geographies.
  • Highly organized, strong affinity for automation and prioritization.

  

PREFERRED EXPERIENCE:  

  • 8+ years of strong experience in Physical Design Implementation/Automation and optimization for quality.
  • Experienced in deploying and implementing ML techniques and algorithms in physical design.
  • Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
  • Scripting language experience: TCL, Perl, Python, Makefile.
  • Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
  • AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.

 

ACADEMIC CREDENTIALS:  

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

#LI-SR4




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER

  

THE ROLE: 

As a member of the PPA optimization team, you will work on new physical design flow methodology, automation and regression to release quality instructions to PD block team and will work closely with the PD tile, integration and CAD teams across various geographies to achieve first pass silicon success.

  

THE PERSON:  

  • A successful person in this role would be able to work in a collaborative team environment working with other physical design teams to find creative ways to accelerate and improve PPA
  • Strong self-driving ability, should have excellent communication skills (both written and oral)

  

KEY RESPONSIBILITIES:  

  • Automation to refine and improve design PPA (Power, Performance, Area), to ensure a high quality design environment
  • Ability to organize and present complex technical information in a crisp and concise manner.
  • Interact with other PPA (equivalent) teams internal to AMD
  • Identify best practices across AMD and industry to update and improve flow/project settings
  • To increase the competitiveness of each stage in AMD design flow
  • Ability to work with multi-level functional teams across various geographies.
  • Highly organized, strong affinity for automation and prioritization.

  

PREFERRED EXPERIENCE:  

  • 8+ years of strong experience in Physical Design Implementation/Automation and optimization for quality.
  • Experienced in deploying and implementing ML techniques and algorithms in physical design.
  • Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
  • Scripting language experience: TCL, Perl, Python, Makefile.
  • Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
  • AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.

 

ACADEMIC CREDENTIALS:  

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

#LI-SR4

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