WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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MTS SILICON DESIGN ENGINEER  

Be a member of the team that plays a significant role in ensuring the quality of next generation SoC’s through structured DFT, Scan Insertion, Memory BIST and Automatic Test Pattern Generation (ATPG) techniques.

Responsibilities include:

Working closely with the DFT Architecture and the DFT design teams to align on Scan and ATPG requirements and successfully implementing the MBIST, Scan, and ATPG at block and SoC level

Working closely with the post silicon teams on pattern validation on silicon and debug. Also work with required stake holders on understanding coverage requirements and making sure meeting the coverage accordingly for each block and then at SoC level.

Requirements:

• Around 8 years of experience in DFT implementation for complex chips
• Experience in block level Scan, ATPG, coverage analysis
• Experience with MBIST insertion and verification at block level and chip level
• Experience with Lint, CDC, Scan DRC checks on RTL
• Exposure to Static timing analysis is a plus.
• Excellent hands-on debug skills and scripting skills are critical.
• Must have good communication skills and the ability to work in a worldwide team environment.
• Knowledge & experience of low power concepts, clock gating, power gating is a plus

Qualifications:

B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering

Location - Hyderabad 

#LI-MC1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  

Be a member of the team that plays a significant role in ensuring the quality of next generation SoC’s through structured DFT, Scan Insertion, Memory BIST and Automatic Test Pattern Generation (ATPG) techniques.

Responsibilities include:

Working closely with the DFT Architecture and the DFT design teams to align on Scan and ATPG requirements and successfully implementing the MBIST, Scan, and ATPG at block and SoC level

Working closely with the post silicon teams on pattern validation on silicon and debug. Also work with required stake holders on understanding coverage requirements and making sure meeting the coverage accordingly for each block and then at SoC level.

Requirements:

• Around 8 years of experience in DFT implementation for complex chips
• Experience in block level Scan, ATPG, coverage analysis
• Experience with MBIST insertion and verification at block level and chip level
• Experience with Lint, CDC, Scan DRC checks on RTL
• Exposure to Static timing analysis is a plus.
• Excellent hands-on debug skills and scripting skills are critical.
• Must have good communication skills and the ability to work in a worldwide team environment.
• Knowledge & experience of low power concepts, clock gating, power gating is a plus

Qualifications:

B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering

Location - Hyderabad 

#LI-MC1