Hyderabad, Pakistan
Not specified
Internship
Office work
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
MTS SILICON DESIGN ENGINEER
THE ROLE:
This is an exciting opportunity to work in the AMD SOC Verification Team as a Member of Technical Staff Verification Engineer. The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and participate in silicon bring up.
We are specifically looking for candidates who have experience with verification of PCIE
Responsibilities:
-Create block level verification plan, test plans and full chip test plan
-Develop block level test bench and tests in UVM methodology including scoreboard
-Work on subsystem level verification
-Work with designers to get coverage closure
-Port the block level tests to full chip test bench
-Integrate VIPs as needed
-Work with software, validation and emulation teams as needed
-Work on other aspects of verification like CDC, gate simulation
-Work on lab bring up and silicon validation
Requirements:
-Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
-Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and functional coverage with design team
-Good understanding of object oriented programming concepts
-Prior experience with PCIE Protocol Gen3 and above
-Prior experience in verifying is system/sub system level involving multiple blocks
-Prior experience with protocols such as AXI, APB, AHB etc.
-Programming in scripting languages like Python, TCL and Perl
-Excellent communication skills
-Good problem solving skills and analytical ability
-Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc.
Desirable Requirements:
-Exposure to formal verification methodologies
-Prior experience with verifying PCIE Bridges with DMA
-System level understanding of PCIE based systems
-Understanding of ARM architecture and assembly language programming
-Prior experience in integrating Verification IPs (VIP) & UVC in verification environment
-Prior experience in bringing up gate level simulation and debugging issues
-Prior experience with dynamic CDC simulations
-Understanding of FPGA architecture
-Experience with working on Serdes interfaces such as PCIE, Ethernet
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering with 9 -12 years of relevant experience
#LI-SR5
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
MTS SILICON DESIGN ENGINEER
THE ROLE:
This is an exciting opportunity to work in the AMD SOC Verification Team as a Member of Technical Staff Verification Engineer. The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and participate in silicon bring up.
We are specifically looking for candidates who have experience with verification of PCIE
Responsibilities:
-Create block level verification plan, test plans and full chip test plan
-Develop block level test bench and tests in UVM methodology including scoreboard
-Work on subsystem level verification
-Work with designers to get coverage closure
-Port the block level tests to full chip test bench
-Integrate VIPs as needed
-Work with software, validation and emulation teams as needed
-Work on other aspects of verification like CDC, gate simulation
-Work on lab bring up and silicon validation
Requirements:
-Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
-Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and functional coverage with design team
-Good understanding of object oriented programming concepts
-Prior experience with PCIE Protocol Gen3 and above
-Prior experience in verifying is system/sub system level involving multiple blocks
-Prior experience with protocols such as AXI, APB, AHB etc.
-Programming in scripting languages like Python, TCL and Perl
-Excellent communication skills
-Good problem solving skills and analytical ability
-Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc.
Desirable Requirements:
-Exposure to formal verification methodologies
-Prior experience with verifying PCIE Bridges with DMA
-System level understanding of PCIE based systems
-Understanding of ARM architecture and assembly language programming
-Prior experience in integrating Verification IPs (VIP) & UVC in verification environment
-Prior experience in bringing up gate level simulation and debugging issues
-Prior experience with dynamic CDC simulations
-Understanding of FPGA architecture
-Experience with working on Serdes interfaces such as PCIE, Ethernet
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering with 9 -12 years of relevant experience
#LI-SR5
