WHAT YOU DO AT AMD CHANGES EVERYTHING

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MTS SILICON DESIGN ENGINEER  

THE ROLE: 

The verification team at AMD is looking for a Senior Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs.

Responsibilities:

Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications

Interact with architects and design engineers to create a comprehensive verification testplan

Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner

Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools

Debug tests with design engineers to deliver functionally correct design blocks

Identify and write coverage measures for stimulus quality improvements

Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

Job Qualifications

• Requires BS or MS or PhD in Electrical Engineering, Computer Engineering or Computer Science or related equivalent
• Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs
• Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
• Strong understanding of different phases of ASIC and/or full custom chip development is required
• Experience in block level NOC (Net work on Chip) verification is a plus
• Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus
• Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance SOCs, VLSI designs and/or FPGAs is a plus
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus
• Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus
• Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus

Special Qualifications: Must have at least 1 year of prior work experience in each of the following:

1. Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog;
2. Test plan development and test writing;
3. Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip;
4. Functional coverage writing, coverage collection and analysis, coverage closure;
5. Writing System Verilog assertions and assertion based verification; and,
6. Running regressions, automation using scripting languages such as PERL and verification closure.

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering with 9-12 years of experience
• #LI-SR5

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  

THE ROLE: 

The verification team at AMD is looking for a Senior Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs.

Responsibilities:

Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications

Interact with architects and design engineers to create a comprehensive verification testplan

Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner

Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools

Debug tests with design engineers to deliver functionally correct design blocks

Identify and write coverage measures for stimulus quality improvements

Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

Job Qualifications

• Requires BS or MS or PhD in Electrical Engineering, Computer Engineering or Computer Science or related equivalent
• Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs
• Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
• Strong understanding of different phases of ASIC and/or full custom chip development is required
• Experience in block level NOC (Net work on Chip) verification is a plus
• Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus
• Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance SOCs, VLSI designs and/or FPGAs is a plus
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus
• Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus
• Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus

Special Qualifications: Must have at least 1 year of prior work experience in each of the following:

1. Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog;
2. Test plan development and test writing;
3. Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip;
4. Functional coverage writing, coverage collection and analysis, coverage closure;
5. Writing System Verilog assertions and assertion based verification; and,
6. Running regressions, automation using scripting languages such as PERL and verification closure.

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering with 9-12 years of experience
• #LI-SR5