MTS Silicon Design Engineer (IP/SOC Verification Engineer of 7+ years experience)

Jun 06, 2024
Hyderabad, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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MTS SILICON DESIGN ENGINEER 

 

THE ROLE: 

The focus of this role is to provide technical leadership and contribution on high performance IP/SOC design verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of the design.   

 

THE PERSON: 

  • Should have proven track record on driving strategies and successful IP/SOC verification execution.
  • Should be a strong team player and should have excellent communication and leadership skills and experience collaborating with other engineers located in different sites/time zones.
  • Should have strong analytical and problem-solving skills and should be willing to learn and ready to take on problems.
  • Should have proven track record in technical leadership of teams. This includes planning, execution, tracking, verification closure, and delivery to programs.

 

KEY RESPONSIBILITIES:

  • Collaborate with architects and designers to understand the design and plan verification strategies.
  • Test plan documentation.
  • Effort estimation for the planned verification strategies.
  • Develop directed and random tests.
  • Ownership of regression testing and failure debug to determine the root cause; work with designers to resolve design defects. 
  • Review and closure of functional and code coverage.

 

PREFERRED EXPERIENCE:

  • Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS.
  • Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
  • Working experience with AMBA protocols like AHB/AXI/APB.
  • Understanding of memory controller protocols (DDR*, LPDDR*).
  • Experience with scripting language experience like Perl, Python is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
  • Experience with silicon debug at the tester and board level, is a plus.

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

 

#LI-RP1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER 

 

THE ROLE: 

The focus of this role is to provide technical leadership and contribution on high performance IP/SOC design verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of the design.   

 

THE PERSON: 

  • Should have proven track record on driving strategies and successful IP/SOC verification execution.
  • Should be a strong team player and should have excellent communication and leadership skills and experience collaborating with other engineers located in different sites/time zones.
  • Should have strong analytical and problem-solving skills and should be willing to learn and ready to take on problems.
  • Should have proven track record in technical leadership of teams. This includes planning, execution, tracking, verification closure, and delivery to programs.

 

KEY RESPONSIBILITIES:

  • Collaborate with architects and designers to understand the design and plan verification strategies.
  • Test plan documentation.
  • Effort estimation for the planned verification strategies.
  • Develop directed and random tests.
  • Ownership of regression testing and failure debug to determine the root cause; work with designers to resolve design defects. 
  • Review and closure of functional and code coverage.

 

PREFERRED EXPERIENCE:

  • Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS.
  • Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
  • Working experience with AMBA protocols like AHB/AXI/APB.
  • Understanding of memory controller protocols (DDR*, LPDDR*).
  • Experience with scripting language experience like Perl, Python is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
  • Experience with silicon debug at the tester and board level, is a plus.

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

 

#LI-RP1

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