MTS Silicon Design Engineer (IR/EM Power Lead )

Jan 26, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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MTS SILICON DESIGN ENGINEER 

 

THE ROLE: 

The focus of this role is to plan robust on die power delivery network and ensure full chip IR/EM signoff, partiticipate in generating full chip power rollup and low power signoff actitivites for custom ASICs.

 

THE PERSON: 

You have a passion for modern, complex custom ASICs with focus on physical design and signoffs in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

  • Drive full chip IR/EM convergence on multiple ASICs across different technology nodes
  • Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design
  • Work closely with CAD team to come up with new flows and methodologies in the power integrity domain
  • Work on PTPX and Power Artist for power estimation and optimization
  • Work on low power signoff activities using VLCP

 

PREFERRED EXPERIENCE: 

  • Proficient in full chip IR/EM signoff using Redhawk tools 
  • Proficient in coming up with power grid spec and debugging power integrity issues
  • Proficient in PTPX and Power Artist.
  • Experience in VCLP for low power singoff
  • Experienced with Tcl and Perl. Phython would be added advantage  
  • Exposure to leadership or mentorship is an asset  

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering with 10+Yrs 

 

# LI-SR4




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER 

 

THE ROLE: 

The focus of this role is to plan robust on die power delivery network and ensure full chip IR/EM signoff, partiticipate in generating full chip power rollup and low power signoff actitivites for custom ASICs.

 

THE PERSON: 

You have a passion for modern, complex custom ASICs with focus on physical design and signoffs in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

  • Drive full chip IR/EM convergence on multiple ASICs across different technology nodes
  • Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design
  • Work closely with CAD team to come up with new flows and methodologies in the power integrity domain
  • Work on PTPX and Power Artist for power estimation and optimization
  • Work on low power signoff activities using VLCP

 

PREFERRED EXPERIENCE: 

  • Proficient in full chip IR/EM signoff using Redhawk tools 
  • Proficient in coming up with power grid spec and debugging power integrity issues
  • Proficient in PTPX and Power Artist.
  • Experience in VCLP for low power singoff
  • Experienced with Tcl and Perl. Phython would be added advantage  
  • Exposure to leadership or mentorship is an asset  

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering with 10+Yrs 

 

# LI-SR4

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