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MTS SILICON DESIGN ENGINEER  

• THE ROLE:

   

  The Display Controller team within the Radeon Technologies Group (RTG) is looking for a highly experienced Design professional with strong industry experience to join the IP deployment support team.   As one of the major IP blocks with AMD, the Display Controller IP is delivered into leading edge discrete GPU, APU and semi-custom SOC programs who's execution teams spans the globe.  The Display IP is one of the foundational IP's within AMD and is incorporated in all AMD SOC's which feature direct connectivity to a display device through Display Port, HDMI or USB-C connectors. 

   

  As a proven leader, the candidate would work closely with AMD central CAD, SOC Architecture and IP Design teams to ensure the unique requirements of the Display IP and IP/SOC delivery are well represented.   Such solutions are expected to be sustainable across multiple business units and require close collaboration with key technical leads across the organization to ensure successful program execution. 

   

  As a member of the IP team, the candidate would be responsible for identifying and executing sustainable technical solutions to enable integration of the Display IP design collateral into AMD SOC environments.  This position would require the individual to draw upon proven industry design experiences to ensure successful program execution.

   

  KEY RESPONSIBILITIES:

  • Understand the functional and performance requirements of the Display IP within an APU and dGPU SOC
  • Drive IP/SOC design infra decisions to ensure consumption within the context of the SOC.
  • Provide guidance and/or act as a liaison between IP and SOC design teams for synthesis and physical layout issues 
  • Scope requirements and resources to meet project schedules
  • Provide hands on leadership of a small team of Engineers/Engineers in Training as required to meet program development goals
  • Signoff IP quality for delivery into SOC
  • Effectively communicate with multi-disciplined teams located across the globe
  • Gather, attend and present into technical status meetings on a weekly/bi-weekly basis

   

  PREFERRED EXPERIENCE:

  • Proven RTL design experience on large ASIC development projects
  • Strong background working with industry standard synthesis tools, flows and back end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc)
  • Strong background in Verilog, System Verilog and/or C/C++/OO coding techniques
  • Experience working with UVM, OVM or equivalent is an asset.
  • Strong analytical skills and attention to detail
  • Excellent written and communication skills
  • Experience with display/display related technologies is an asset
  • Understanding of the IP integration and interactions within an SOC
  • Must be a self-starter and able to independently drive tasks to completion
  • Demonstrates the ability to debug issues and quickly identify viable solutions
  • Team player with proven leadership skills

    

  ACADEMIC EXPERIENCE:

  • Min. Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  

• THE ROLE:

   

  The Display Controller team within the Radeon Technologies Group (RTG) is looking for a highly experienced Design professional with strong industry experience to join the IP deployment support team.   As one of the major IP blocks with AMD, the Display Controller IP is delivered into leading edge discrete GPU, APU and semi-custom SOC programs who's execution teams spans the globe.  The Display IP is one of the foundational IP's within AMD and is incorporated in all AMD SOC's which feature direct connectivity to a display device through Display Port, HDMI or USB-C connectors. 

   

  As a proven leader, the candidate would work closely with AMD central CAD, SOC Architecture and IP Design teams to ensure the unique requirements of the Display IP and IP/SOC delivery are well represented.   Such solutions are expected to be sustainable across multiple business units and require close collaboration with key technical leads across the organization to ensure successful program execution. 

   

  As a member of the IP team, the candidate would be responsible for identifying and executing sustainable technical solutions to enable integration of the Display IP design collateral into AMD SOC environments.  This position would require the individual to draw upon proven industry design experiences to ensure successful program execution.

   

  KEY RESPONSIBILITIES:

  • Understand the functional and performance requirements of the Display IP within an APU and dGPU SOC
  • Drive IP/SOC design infra decisions to ensure consumption within the context of the SOC.
  • Provide guidance and/or act as a liaison between IP and SOC design teams for synthesis and physical layout issues 
  • Scope requirements and resources to meet project schedules
  • Provide hands on leadership of a small team of Engineers/Engineers in Training as required to meet program development goals
  • Signoff IP quality for delivery into SOC
  • Effectively communicate with multi-disciplined teams located across the globe
  • Gather, attend and present into technical status meetings on a weekly/bi-weekly basis

   

  PREFERRED EXPERIENCE:

  • Proven RTL design experience on large ASIC development projects
  • Strong background working with industry standard synthesis tools, flows and back end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc)
  • Strong background in Verilog, System Verilog and/or C/C++/OO coding techniques
  • Experience working with UVM, OVM or equivalent is an asset.
  • Strong analytical skills and attention to detail
  • Excellent written and communication skills
  • Experience with display/display related technologies is an asset
  • Understanding of the IP integration and interactions within an SOC
  • Must be a self-starter and able to independently drive tasks to completion
  • Demonstrates the ability to debug issues and quickly identify viable solutions
  • Team player with proven leadership skills

    

  ACADEMIC EXPERIENCE:

  • Min. Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering