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MTS SILICON DESIGN ENGINEER  

Job Description:

As a Full-Chip Floor Planning Engineer, you will play a crucial role in the physical design and implementation of advanced semiconductor chips. Working closely with RTL designers, physical design teams, and other cross-functional groups, you will be responsible for full-chip floor planning, enabling efficient design layouts, and optimizing the placement of major functional blocks. This position requires a solid understanding of physical design and chip architecture, as well as experience in floor planning tools and methodologies for high-performance and low-power design.

Technical Requirements

• Proven experience in top level floor planning/block partition which includes physical partition, pin/feedthrough placements and repeaters assignments.

•        Experience in SOC floorplan aspects like FullChip clock spine distribution, analog integration, push down macros, GPIOs.

• Proficiency in EDA tools such as Cadence, Synopsys ICC, Calibre, etc.
• Strong scripting skills in Tcl, Perl, or Python for automation
• In-depth knowledge of upf, floor planning concepts, including chip partitioning, placement, and routing methodologies.
• Experience with power, timing, and area optimization techniques
• Familiarity with design rule check (DRC) requirements.

Responsibilities

• Lead the floor planning process from RTL to GDSII, optimizing block placement, chip partitioning, and routing feasibility to ensure timing, power, and area constraints are met.
• Collaborate with RTL, block-level, and physical design teams to integrate IPs, macros, and other design components efficiently at the top level
• Work on area and power optimization techniques to achieve a highly efficient chip layout. Perform what-if analyses to evaluate trade-offs and optimize design parameters.
• Interface with architecture, package, and timing teams to align on chip-level requirements and ensure the physical design meets performance and design intent.
• Identify potential design issues early in the floor planning process and collaborate with stakeholders to develop and implement mitigation strategies
• Develop, enhance, and maintain custom scripts to automate repetitive tasks within the floor planning flow, ensuring efficiency and accuracy.

#LI-SR4

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  

Job Description:

As a Full-Chip Floor Planning Engineer, you will play a crucial role in the physical design and implementation of advanced semiconductor chips. Working closely with RTL designers, physical design teams, and other cross-functional groups, you will be responsible for full-chip floor planning, enabling efficient design layouts, and optimizing the placement of major functional blocks. This position requires a solid understanding of physical design and chip architecture, as well as experience in floor planning tools and methodologies for high-performance and low-power design.

Technical Requirements

• Proven experience in top level floor planning/block partition which includes physical partition, pin/feedthrough placements and repeaters assignments.

•        Experience in SOC floorplan aspects like FullChip clock spine distribution, analog integration, push down macros, GPIOs.

• Proficiency in EDA tools such as Cadence, Synopsys ICC, Calibre, etc.
• Strong scripting skills in Tcl, Perl, or Python for automation
• In-depth knowledge of upf, floor planning concepts, including chip partitioning, placement, and routing methodologies.
• Experience with power, timing, and area optimization techniques
• Familiarity with design rule check (DRC) requirements.

Responsibilities

• Lead the floor planning process from RTL to GDSII, optimizing block placement, chip partitioning, and routing feasibility to ensure timing, power, and area constraints are met.
• Collaborate with RTL, block-level, and physical design teams to integrate IPs, macros, and other design components efficiently at the top level
• Work on area and power optimization techniques to achieve a highly efficient chip layout. Perform what-if analyses to evaluate trade-offs and optimize design parameters.
• Interface with architecture, package, and timing teams to align on chip-level requirements and ensure the physical design meets performance and design intent.
• Identify potential design issues early in the floor planning process and collaborate with stakeholders to develop and implement mitigation strategies
• Develop, enhance, and maintain custom scripts to automate repetitive tasks within the floor planning flow, ensuring efficiency and accuracy.

#LI-SR4